EP2AGX65DF29I5N Altera, EP2AGX65DF29I5N Datasheet - Page 297

• Manufacturer Part Number: EP2AGX65DF29I5N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29I5N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
Fast Passive Parallel Configuration
Figure 9–5. FPP Configuration Timing Waveform with Decompression or Design Security Enabled
Notes to
(1) Use this timing waveform when you use the decompression and/or design security features.
(2) The beginning of this waveform shows the device in user-mode. In user-mode, nCONFIG, nSTATUS, and CONF_DONE are at logic high levels. When
(3) After power-up, the Arria II GX device holds nSTATUS low for the time of the POR delay.
(4) After power-up, before and during configuration, CONF_DONE is low.
(5) Two DCLK falling edges are required after CONF_DONE goes high to begin the initialization of the device.
(6) If required, you can pause DCLK by holding it low. When DCLK restarts, the external host must provide data on the DATA[7..0] pins prior to
(7) Do not leave DCLK floating after configuration. You can drive it high or low, whichever is more convenient.
(8) DATA[7..1] are available as user I/O pins after configuration. The state of these pins depends on the dual-purpose pin settings. For Arria II GX
December 2010 Altera Corporation
CONF_DONE
nCONFIG is pulled low, a reconfiguration cycle begins.
sending the first DCLK rising edge.
devices, DATA[0] is a dedicated pin that is used for both the PS and AS configuration modes and is not available as a user I/O pin after
configuration. For Arria II GZ devices, DATA[0] is available as a user I/O pin after configuration.
nSTATUS (3)
INIT_DONE
DATA[7..0]
nCONFIG
Figure
User I/O
DCLK
(4)
9–5:
t
t
CF2CD
CFG
t
CF2ST1
t
CF2ST0
Figure 9–5
MAX II device or microprocessor as an external host. This waveform shows timing
when you enable the decompression, the design security features, or both.u
t
CF2CK
t
ST2CK
t
STATUS
t
High-Z
DSU
1
2
Byte 0
t
DH
shows the timing waveform for an FPP configuration when using a
3
4
1
t
CH
2
t
Byte 1
CLK
t
t
CL
DH
3
4
(6)
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Byte 2
1
Byte (n-1)
3
(5)
4
Byte n
t
CD2UM
(Note
1),
(7)
(8)
User Mode
User Mode
(2)
9–17