EP2AGX65DF29I5N Altera, EP2AGX65DF29I5N Datasheet - Page 339

• Manufacturer Part Number: EP2AGX65DF29I5N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29I5N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
Dedicated Remote System Upgrade Circuitry
December 2010 Altera Corporation
User Watchdog Timer
1
Table 9–22. Control Register Contents after an Error or Reconfiguration Trigger Condition
Capture operations during factory configuration access the contents of the update
register. This feature is used by the user logic to verify that the page address and
watchdog timer settings were written correctly. Read operations in application
configurations access the contents of the control register. This information is used by
the user logic in the application configuration.
The user watchdog timer prevents a faulty application configuration from stalling the
device indefinitely. The system uses the timer to detect functional errors after an
application configuration is successfully loaded into the Arria II device.
To allow remote system upgrade dedicated circuitry to reset the watchdog timer, you
must assert the RU_nRSTIMER signal active for a minimum of 250 ns. This is equivalent
to strobing the reset_timer input of the ALTREMOTE_UPDATE megafunction high
for a minimum of 250 ns.
The user watchdog timer is a counter that counts down from the initial value loaded
into the remote system upgrade control register by the factory configuration. The
counter is 29 bits wide and has a maximum count value of 2
user watchdog timer value, specify only the most significant 12 bits. The granularity
of the timer setting is 2
10-MHz internal oscillator.
oscillator.
Table 9–23. 10-MHz Internal Oscillator Specifications—Preliminary
The user watchdog timer begins counting after the application configuration enters
device user mode. This timer must be periodically reloaded or reset by the application
configuration before the timer expires by asserting RU_nRSTIMER. If the application
configuration does not reload the user watchdog timer before the count expires, a
time-out signal is generated by the remote system upgrade dedicated circuitry. The
time-out signal tells the remote system upgrade circuitry to set the user watchdog
timer status bit (Wd) in the remote system upgrade status register and reconfigures the
device by loading the factory configuration.
During the configuration cycle of the device, the user watchdog timer is not enabled.
Errors during configuration are detected by the CRC engine. Also, the timer is
disabled for factory configurations. Functional errors should not exist in the factory
configuration because it is stored and validated during production and is never
updated remotely.
(Part 2 of 2)
CRC error
Wd time out
Reconfiguration Error/Trigger
Minimum
4.3
1
7
cycles. The cycle time is based on the frequency of the
Table 9–23
Typical
5.3
Arria II Device Handbook Volume 1: Device Interfaces and Integration
lists the operating range of the 10-MHz internal
Control Register Setting Remote Update
Maximum
10
All bits are 0
All bits are 0
29
. When specifying the
Units
MHz
9–59