EP2AGX65DF29I5N Altera, EP2AGX65DF29I5N Datasheet - Page 561

• Manufacturer Part Number: EP2AGX65DF29I5N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29I5N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 3: Configuring Multiple Protocols and Data Rates in Arria II Devices
Sharing CMU PLLs
Sharing CMU PLLs
December 2010 Altera Corporation
Multiple Channels Sharing a CMU PLL
1
1
Asserting the cal_blk_powerdown port affects the calibration circuit on all transceiver
channels connected to the calibration block.
Each Arria II GX and GZ transceiver block contains two CMU PLLs. When you create
multiple transceiver channel instances and intend to combine them in the same
transceiver block, the Quartus II software checks whether a single CMU PLL can be
used to provide clock outputs for the transmitter side of the channel instances. If a
single CMU PLL is not sufficient, the Quartus II software attempts to combine the
channel instances using two CMU PLLs. Otherwise, the Quartus II software issues a
Fitter error.
The following two sections describe the ALTGX instance requirements to enable the
Quartus II software to share the CMU PLL.
Only channels combined within the same transceiver block can share the two
CMU PLLs available in a transceiver block.
To enable the Quartus II software to share the same CMU PLL for multiple channels,
the following parameters in the channel instantiations must be identical:
■
■
■
■
■
Each channel instance can have a different local divider setting. Different settings are
useful when you intend to run each channel within the transceiver block at different
data rates that are derived from the same base data rate using the local divider values
/1, /2, and /4. This is shown in
Example 1
Consider a design with four instances in a Receiver and Transmitter configuration in
the same transceiver block at the following serial data rates. Assume that each
instance contains a channel, is driven from the same clock source, and has the same
CMU PLL bandwidth settings.
Table 3–1
Table 3–1. Configuration for Example 1 for Arria II Devices (Part 1 of 2)
User-Created
Instance Name
inst0
inst1
Base data rate (the CMU PLL is configured for this data rate)
CMU PLL bandwidth setting
Reference clock frequency
Input reference clock pin
pll_powerdown port of the ALTGX instances must be driven from the same logic
lists the configuration for Example 1.
Number of Channels
1
1
ALTGX MegaWizard Plug-In Manager Settings
Example
Receiver and Transmitter
Receiver and Transmitter
1.
Configuration
Arria II Device Handbook Volume 2: Transceivers
Effective Data Rate
0.9375
(Gbps)
3.75
3–3