EP2AGX65DF29I5N Altera, EP2AGX65DF29I5N Datasheet - Page 399

• Manufacturer Part Number: EP2AGX65DF29I5N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29I5N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 1: Transceiver Architecture in Arria II Devices
Transmitter Channel Datapath
December 2010 Altera Corporation
f
Figure 1–12
Figure 1–12. TX Phase Compensation FIFO
Notes to
(1) The tx_phase_comp_fifo_error is optional and available in all functional modes. This signal is asserted high to
(2) Use this optional clock for the FIFO write clock if you instantiate the tx_coreclk port in the ALTGX MegaWizard
(3) The tx_clkout low-speed parallel clock is from the local clock divider from the associated transmitter channel and
(4) The coreclkout clock is from the CMU0 block of the associated transceiver block or the master transceiver block for
For more information about TX phase compensation FIFO clocking, refer to the
“Limitation of the Quartus II Software-Selected Transmitter Phase Compensation
FIFO Write (or Read) Clocks” section in the
chapter.
An optional tx_phase_comp_fifo_error port is available in all functional modes and
is asserted high in an overflow or underflow condition. If this signal is asserted,
ensure that there is 0 PPM difference between the TX phase compensation FIFO read
and write clocks.
The output of this block can go to any of the following blocks:
■
■
■
Byte serializer—If you enable this block.
8B/10B encoder—If you disable the byte serializer, but enable the 8B/10B encoder
and your channel width is either 8 or 16 bits.
Serializer—If you disable both the byte serializer and the 8B/10B encoder, or if
you use low-latency PCS bypass mode.
indicate an overflow or underflow condition.
Plug-In Manager, regardless of the channel configurations. Otherwise, the same clock used for the read clock is also
used for the write clock. Ensure that there is 0 parts per million (PPM) frequency difference between the tx_coreclk
clock and the read clock of the FIFO.
is used in non-bonded configurations.
×4 bonded or ×8 bonded channel configurations, respectively.
Figure
shows the datapath and clocking of the TX phase compensation FIFO.
1–12:
tx_coreclk (2)
Interface (tx_datain)
Data Input from
Fabric of PIPE
the FPGA
wr_clk
Compensation
TX Phase
FIFO
rd_clk
Transceiver Clocking in Arria II Devices
Arria II Device Handbook Volume 2: Transceivers
Encoder or Serializer
tx_phase_comp_fifo_error (1)
the Byte Serializer
Data Output to
or the 8B/10B
tx_clkout (3)
coreclkout (4)
1–13