EP2AGX65DF29I5N Altera, EP2AGX65DF29I5N Datasheet - Page 451

• Manufacturer Part Number: EP2AGX65DF29I5N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29I5N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 1: Transceiver Architecture in Arria II Devices
Functional Modes
Table 1–16. powerdn [1:0] Port Power State Functions and Descriptions for Arria II Devices
December 2010 Altera Corporation
powerdn [1:0]
Values
2’b00
2’b01
2’b10
2’b11
1
Power
State
P0s
P0
P1
P2
Besides transferring data, control, and status signals between the PHY-MAC layer and
the transceiver, the PIPE interface block implements the following functions required
in a PIPE-compliant physical layer device:
■
■
■
■
■
■
The following subsections describe each Arria II GX and GZ transceiver function.
Power State Management
The PCIe specification defines four power states that the physical layer device must
support to minimize power consumption:
■
■
The PCIe specification provides the mapping of these power states to the long-term
sample storage module (LTSSM) states specified in the PCIe Base Specification 2.0.
The PHY-MAC layer is responsible for implementing the mapping logic between the
LTSSM states and the four power states in the PCIe-compliant PHY.
The PIPE interface in Arria II GX and GZ transceivers provide an input port
(powerdn[1:0]) to set the transceivers in one of the four power states, as shown in
Table
When the device transitions from the P0 power state to lower power states (P0s, P1,
and P2), the PCIe specification requires the physical layer device to implement power
saving measures. Arria II GX and GZ transceivers do not implement these power
saving measures except when putting the transmitter buffer in electrical idle in the
lower power states.
Normal operation mode
Low recovery time saving state
High recovery time power saving state
Lowest power saving state
Manages the PIPE power states
Forces the transmitter buffer in the electrical idle state
Initiates the receiver detect sequence
Controls 8B/10B encoder disparity when transmitting compliance pattern
Indicates completion of various PHY functions, such as receiver detection and
power state transitions on the pipephydonestatus signal
Encodes receiver status and error conditions on the pipestatus[2:0] signal as
specified in the PIPE specification
P0 is the normal operation state during which packet data is transferred on the
PCIe link.
P0s, P1, and P2 are low-power states into which the physical layer must transition
as directed by the PHY-MAC layer to minimize power consumption.
1–16.
Description
Transmits normal data, transmits electrical idle, or
enters into loopback mode
Only transmits electrical idle
Transmitter buffer is powered down and can perform a
receiver detect while in this state
Transmits electrical idle or a beacon to wake up the
downstream receiver
Arria II Device Handbook Volume 2: Transceivers
Function
1–65