EP2AGX65DF29I5N Altera, EP2AGX65DF29I5N Datasheet - Page 141

• Manufacturer Part Number: EP2AGX65DF29I5N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29I5N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 5: Clock Networks and PLLs in Arria II Devices
PLLs in Arria II Devices
Figure 5–30. Automatic Clock Switchover Circuit Block Diagram for Arria II Devices
December 2010 Altera Corporation
1
inclk0
inclk1
Arria II PLLs support a fully configurable clock switchover capability.
shows the block diagram of the switchover circuit built into the PLL. When the
current reference clock is not present, the clock sense block automatically switches to
the backup clock for PLL reference. The clock switchover circuit also sends out three
status signals—clkbad[0], clkbad[1], and activeclock—from the PLL to implement
a custom switchover circuit in the logic array. You can select a clock source as the
backup clock by connecting it to the inclk1 port of the PLL in your design.
Automatic Clock Switchover Mode
Use the switchover circuitry to automatically switch between inclk0 and inclk1
when the current reference clock to the PLL stops toggling. For example, in
applications that require a redundant clock with the same frequency as the reference
clock, the switchover state machine generates a signal (clksw) that controls the
multiplexer select input, as shown in
reference clock for the PLL. When you use the automatic switchover mode, you can
switch back and forth between the inclk0 and inclk1 clocks any number of times,
when one of the two clocks fails and the other clock is available.
When you use the automatic clock switchover mode, the following requirements
must be satisfied:
■
■
If the current clock input stops toggling while the other clock is also not toggling,
switchover is not initiated and the clkbad[0:1] signals are not valid. Also, if both
clock inputs are not the same frequency, but their period difference is 100%, the clock
sense block detects when a clock stops toggling, but the PLL may lose lock after the
switchover is completed and requires time to relock.
Altera recommends resetting the PLL with the areset signal to maintain the phase
relationships between the PLL input and output clocks when you use clock
switchover.
Both clock inputs must be running.
The period of the two clock inputs can differ by no more than 100% (2×).
muxout
clksw
n Counter
Sense
Clock
refclk
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Figure
Switchover
Machine
State
5–30. In this case, inclk1 becomes the
Clock Switch
Control Logic
PFD
fbclk
clkbad0
clkbad1
activeclock
clkswitch
Figure 5–30
5–37