EP2AGX65DF29I5N Altera, EP2AGX65DF29I5N Datasheet - Page 311

• Manufacturer Part Number: EP2AGX65DF29I5N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29I5N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
PS Configuration
Figure 9–14. PS Configuration Using a USB-Blaster, EthernetBlaster, EthernetBlaster II, MasterBlaster, ByteBlaster II,
or ByteBlasterMV Cable
Notes to
(1) Connect the pull-up resistor to the same supply voltage, V
(2) You only need the pull-up resistors on DATA0 and DCLK if the download cable is the only configuration scheme used on your board. This ensures
(3) The MSEL pin settings vary for different configuration voltage standards and POR delays. To connect MSEL[3..0]for an Arria II GX device, refer
(4) In the ByteBlasterMV cable, pin 6 is a no connect. In the USB-Blaster and ByteBlaster II cables, this pin is connected to nCE when it is used for
December 2010 Altera Corporation
EthernetBlaster, EthernetBlaster II, MasterBlaster, ByteBlaster II, or ByteBlasterMV cable.
that DATA0 and DCLK are not left floating after configuration. For example, if you are also using a configuration device, you do not need the pull-up
resistors on DATA0 and DCLK.
to
AS programming; otherwise, it is a no connect.
Table 9–6 on page
Figure
V
CCIO
9–14:
/V
(1)
CCPGM
10
(2)
kΩ
V
CCIO
10
9–9. To connect MSEL[2..0] for an Arria II GZ device, refer to
(2)
Figure 9–14
EthernetBlaster, EthernetBlaster II, MasterBlaster, ByteBlaster II, or ByteBlasterMV
cable.
/V
(1)
You can use a download cable to configure multiple Arria II devices by connecting the
nCEO pin of each device to the nCE pin of the subsequent device. The nCE pin of the first
device is connected to GND, while its nCEO pin is connected to the nCE of the next
device in the chain. The nCE input of the last device comes from the previous device,
while its nCEO pin is left floating. All other configuration pins (nCONFIG, nSTATUS, DCLK,
DATA0, and CONF_DONE) are connected to every device in the chain. Because all
CONF_DONE pins are tied together, all devices in the chain initialize and enter user mode
at the same time.
In addition, because the nSTATUS pins are tied together, the entire chain halts
configuration if any device detects an error. The Auto-restart configuration after
error option does not affect the configuration cycle because you must manually restart
configuration in the Quartus II software when an error occurs.
kΩ
V
CCPGM
CCIO
/V
(1)
CCPGM
10
kΩ
shows a PS configuration for Arria II devices using a USB-Blaster,
GND
(3)
CCIO
nCE
DCLK
DATA0
nCONFIG
MSEL[n..0]
Arria II Device
for Arria II GX devices or V
CONF_DONE
nSTATUS
nCEO
Arria II Device Handbook Volume 1: Device Interfaces and Integration
V
CCIO
N.C.
Table 9–7 on page
/V
(1)
CCPGM
CCPGM
10
kΩ
V
CCIO
for Arria II GZ devices as the USB-Blaster,
/V
(1)
10
CCPGM
kΩ
Pin 1
9–10.
10-Pin Male Header
Download Cable
(PS Mode)
Shield
GND
V
CCIO
V
IO
/V
CCPGM
(4)
GND
(1)
9–31