EP2AGX65DF29I5N Altera, EP2AGX65DF29I5N Datasheet - Page 173

• Manufacturer Part Number: EP2AGX65DF29I5N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29I5N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 6: I/O Features in Arria II Devices
I/O Structure
December 2010 Altera Corporation
1
Table 6–7. Programmable Current Strength for Arria II GX Devices (Part 2 of 2)
Table 6–8. Programmable Current Strength for Arria II GZ Devices
Altera recommends performing IBIS or SPICE simulations to determine the right
current strength setting for your specific application.
HSTL-12 Class I
HSTL-12 Class II
BLVDS
Notes to
(1) The default current strength setting in the Quartus II software is 50-Ω R
(2) The default current strength setting in the Quartus II software is the current strength shown in brackets [].
3.3-V LVTTL
3.3-V LVCMOS
2.5-V LVCMOS
1.8-V LVCMOS
1.5-V LVCMOS
1.2-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
SSTL-15 Class I
SSTL-15 Class II
HSTL-18 Class I
HSTL-18 Class II
HSTL-15 Class I
HSTL-15 Class II
HSTL-12 Class I
HSTL-12 Class II
Notes to
(1) The default setting in the Quartus II software is 50-
(2) The 3.3-V LVTTL and 3.3-V LVCMOS are supported using V
non-voltage reference and HSTL/SSTL Class I I/O standards. The default setting is 25-Ω R
for HSTL/SSTL Class II I/O standards.
HSTL and SSTL Class I I/O standards. The default setting is 25-
Class II I/O standards.
Table
Table
I/O Standard
6–7:
6–7:
I/O Standard
Arria II Device Handbook Volume 1: Device Interfaces and Integration
I
OH
/ I
Setting (mA) for
Column I/O Pins
12, 10, 8, 6, 4, 2
12, 10, 8, 6, 4, 2
Ω
OL
12, 10, 8, 6, 4
12, 10, 8, 6, 4
12, 10, 8, 6, 4
12, 10, 8, 6, 4
12, 10, 8, 6, 4
R
16, 12, 8, 4
16, 12, 8, 4
16, 12, 8, 4
Current Strength
S
8, 6, 4, 2
12, 10, 8
OCT without calibration for all non-voltage reference and
16, 8
16, 8
16
16
16
16
CCIO
I
OL
for Top, Bottom, and Right I/O Pins
Ω
/ I
and V
R
OH
S
OCT without calibration for HSTL and SSTL
Current Strength Setting (mA)
CCPD
S
OCT without calibration for all
at 3.0 V.
(Note
12, 10, 8
8, 12, 16
16
I
OH
1),
/ I
Setting (mA) for
S
OL
12, 10, 8, 6, 4
12, 10, 8, 6, 4
Row I/O Pins
(2)
OCT without calibration
Current Strength
8, 6, 4, 2
8, 6, 4, 2
12, 8, 4
12, 8, 4
8, 6, 4
8, 6, 4
8, 6, 4
12, 8
16, 8
8, 4
4, 2
(Note 1)
16
—
16
—
—
6–15