EP2AGX65DF29I5N Altera, EP2AGX65DF29I5N Datasheet - Page 510

• Manufacturer Part Number: EP2AGX65DF29I5N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29I5N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

2–20
Table 2–4. Receiver Datapath Clock Frequencies in Non-Bonded Functional Modes Without Rate Matcher for Arria II
Devices
Arria II Device Handbook Volume 2: Transceivers
Note to
(1) Altera also supports CPRI and OBSAI. For more information, refer to
Functional Mode
SONET/SDH OC12
SONET/SDH OC48
Serial RapidIO
Table
HD SDI
3G-SDI
2–4:
(1)
In non-bonded configurations without rate matcher, the CDR in each receiver channel
recovers the serial clock from the received data. The serial recovered clock frequency
is half the configured data rate due to the half-rate CDR architecture. The PMA
receiver divides the serial recovered clock to generate the parallel recovered clock.
The deserializer uses the serial recovered clock in the receiver PMA. The parallel
recovered clock and deserialized data is forwarded to the receiver PCS. The parallel
recovered clock in each channel clocks the word aligner and 8B/10B decoder (if
enabled).
If the configured functional mode does not use the byte deserializer, the parallel
recovered clock also clocks the write side of the receiver phase compensation FIFO. It
is also driven on the rx_clkout port as the FPGA fabric-transceiver interface clock.
You can use the rx_clkout signal to latch the receiver data and status signals in the
FPGA fabric.
If the configured functional mode uses the byte deserializer, the parallel recovered
clock is divided by two. This divide-by-two version of the parallel recovered clock
clocks the read side of the byte deserializer, the byte ordering block (if enabled), and
the write side of the receiver phase compensation FIFO. It is also driven on the
rx_clkout port as the FPGA fabric-transceiver interface clock. You can use the
rx_clkout signal to latch the receiver data and status signals in the FPGA fabric.
Table 2–4
modes without rate matcher.
1.4835 Gbps
3.125 Gbps
2.488 Gbps
1.485 Gbps
2.967 Gbps
1.25 Gbps
2.97 Gbps
Data Rate
622 Mbps
2.5 Gbps
lists the receiver datapath clock frequencies in non-bonded functional
Serial Clock
741.75 MHz
High-Speed
1.5625 GHz
1.4835 Ghz
Frequency
742.5 MHz
1.244 GHz
1.485 GHz
1.25 GHz
625 MHz
311 MHz
AN 610: Implementing CPRI and OBSAI Protocols in Altera
Parallel Clock
Low-Speed
Frequency
148.35
(MHz)
312.5
77.75
148.5
296.7
125
250
311
297
Chapter 2: Transceiver Clocking in Arria II Devices
Serializer (MHz)
FPGA Fabric-Transceiver Interface
Without Byte
148.35
77.75
148.5
Transceiver Channel Datapath Clocking
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December 2010 Altera Corporation
Clock Frequency
Serializer (MHz)
With Byte
156.25
74.175
148.35
155.5
74.25
148.5
62.5
125
Devices.
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