EP2AGX65DF29I5N Altera, EP2AGX65DF29I5N Datasheet - Page 159
EP2AGX65DF29I5N
Manufacturer Part Number
EP2AGX65DF29I5N
Description
IC ARRIA II GX FPGA 65K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
Specifications of EP2AGX65DF29I5N
Number Of Logic Elements/cells
60214
Number Of Labs/clbs
2530
Total Ram Bits
5246
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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AIIGX51006-4.0
Arria II Device Handbook Volume 1: Device Interfaces and Integration
December 2010
December 2010
AIIGX51006-4.0
This chapter describes how Arria
to work in compliance with current and emerging I/O standards and requirements.
With these device features, you can reduce board design interface costs and increase
development flexibility.
Package and die enhancements with dynamic termination and output control provide
best-in-class signal integrity. Numerous I/O features assist high-speed data transfer
into and out of the device, including:
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■
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This chapter includes the following sections:
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Single-ended, non-voltage-referenced, and voltage-referenced I/O standards
Low-voltage differential signaling (LVDS), reduced swing differential signal
(RSDS), mini-LVDS, high-speed transceiver logic (HSTL), and SSTL
Bus LVDS (BLVDS) for Arria II GX devices
Programmable output current strength
Programmable slew rate
Programmable bus-hold
Programmable pull-up resistor
Open-drain output
On-chip series termination (R
On-chip differential termination (R
On-chip parallel termination (R
Dynamic OCT for Arria II GZ devices
Programmable pre-emphasis
Programmable voltage output differential (V
“I/O Standards Support” on page 6–2
“I/O Banks” on page 6–5
“I/O Structure” on page 6–10
“OCT Support” on page 6–19
“Arria II OCT Calibration” on page 6–26
“Termination Schemes for I/O Standards” on page 6–28
“I/O Bank Restrictions” on page 6–36
6. I/O Features in Arria II Devices
S
®
OCT)
II devices provide I/O capabilities that allow you
T
OCT) for Arria II GZ devices
D
OCT)
OD
)
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