EP2AGX65DF29I5N Altera, EP2AGX65DF29I5N Datasheet - Page 229

• Manufacturer Part Number: EP2AGX65DF29I5N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29I5N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 7: External Memory Interfaces in Arria II Devices
Arria II External Memory Interface Features
December 2010 Altera Corporation
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You can either use a static phase offset or a dynamic phase offset to implement the
additional phase shift. The available additional phase shift is implemented in 2s:
complement in Gray-code between the –64 to +63 settings for frequency mode 0, 1, 2,
and 3, and between the –32 to +31 settings for frequency modes 4, 5, 6, and 7. An
additional bit indicates whether the setting has a positive or negative value. The
settings are linear and each phase offset setting adds a delay amount.
For more information about the specified phase-shift settings, refer to the
Datasheet for Arria II
The DQS phase shift is the sum of the DLL delay settings and the user-selected phase
offset settings whose top setting is 64 for frequency modes 0, 1, 2, and 3; 32 for
frequency modes 4, 5, 6, and 7. Therefore, the actual physical offset setting range is 64
or 32 subtracted by the DQS delay settings from the DLL.
If you use this feature, monitor the DQS delay settings to know how many offsets you
can add and subtract in the system. The DQS delay settings output by the DLL are
also Gray-coded.
For example, if the DLL determines that DQS delay settings of 28 are required to
achieve a 30° phase shift in DLL frequency mode 1, you can subtract up to 28 phase
offset settings and add up to 35 phase offset settings to achieve the optimal delay
required. However, if the same DQS delay settings of 28 is required to achieve a 30°
phase shift in DLL frequency mode 4, subtract up to 28 phase offset settings, but only
add up to 3 phase offset settings before the DQS delay settings reach their maximum
settings because DLL frequency mode 4 only uses 5-bit DLL delay settings.
For more information about the value for each step, refer to the
Arria II
When using static phase offset, specify the phase offset amount in the ALTMEMPHY
megafunction as a positive number for addition or a negative number for subtraction.
You can also have a dynamic phase offset that is always added to, subtracted from, or
both added to and subtracted from the DLL phase shift. When you always add or
subtract, you can dynamically input the phase offset amount into the
dll_offset[5..0] port. When you want to both add and subtract dynamically, you
control the addnsub signal in addition to the dll_offset[5..0] signals.
Devices.
Devices.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Device Datasheet for
Device
7–33