EP2AGX65DF29I5N Altera, EP2AGX65DF29I5N Datasheet - Page 29

• Manufacturer Part Number: EP2AGX65DF29I5N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29I5N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

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AIIGX51002-2.0
Logic Array Blocks
Figure 2–1. LAB Structure in Arria II Devices
Arria II Device Handbook Volume 1: Device Interfaces and Integration
December 2010
December 2010
AIIGX51002-2.0
Direct link
interconnect from
adjacent block
Direct link
interconnect to
adjacent block
R20
R4
This chapter describes the features of the logic array block (LAB) in the Arria
fabric. The LAB is composed of basic building blocks known as adaptive logic
modules (ALMs) that you can configure to implement logic functions, arithmetic
functions, and register functions.
This chapter contains the following sections:
■
■
Each LAB consists of ten ALMs, various carry chains, shared arithmetic chains, LAB
control signals, local interconnect, and register chain connection lines. The local
interconnect transfers signals between ALMs in the same LAB. The direct link
interconnect allows the LAB to drive into the local interconnect of its left and right
neighbors. Register chain connections transfer the output of the ALM register to the
adjacent ALM register in the LAB. The Quartus
the LAB or the adjacent LABs, allowing the use of local, shared arithmetic chain, and
register chain connections for performance and area efficiency.
Figure 2–1
“Logic Array Blocks” on page 2–1
“Adaptive Logic Modules” on page 2–5
shows the Arria II LAB structure and the LAB interconnects.
Local Interconnect
2. Logic Array Blocks and Adaptive Logic
LAB
C4
& LABs, & from Above by Row Interconnect
from Either Side by Column Interconnect
C12
Local Interconnect is Driven
Row Interconnects of
Variable Speed & Length
Modules in Arria II Devices
®
MLAB
II Compiler places associated logic in
ALMs
Column Interconnects of
Variable Speed & Length
Direct link
interconnect from
adjacent block
Direct link
interconnect to
adjacent block
®
II core
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