EP2AGX65DF29I5N Altera, EP2AGX65DF29I5N Datasheet - Page 502

• Manufacturer Part Number: EP2AGX65DF29I5N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29I5N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

2–12
Table 2–3. Transmitter Datapath Clock Frequencies in ×4 Bonded Functional Modes for Arria II Devices
Arria II Device Handbook Volume 2: Transceivers
Note to
(1) Altera also supports CPRI ×4 and OBSAI ×4. For more information, refer to
(2) 250 MHz when you enable the PCIe hard IP.
Functional Mode
PCIe ×4 (Gen 1)
PCIe ×4 (Gen 2)
Table
XAUI
2–3:
(1)
In ×4 bonded channel configurations, CMU0_PLL or CMU1_PLL synthesizes the input
reference clock to generate a clock that runs at a frequency of half the configured data
rate. The half-rate clock from either of the CMU PLLs is fed to the CMU0 clock divider
in the CMU0_Channel. Depending on the configured functional mode, the CMU0 clock
divider block generates the high-speed serial clock and low-speed parallel clock. The
serializer in the transmitter channel PMA of the four bonded channels uses the same
low-speed parallel clock and high-speed serial clock from the CMU0 block for their
parallel-in, serial-out operation. The low-speed parallel clock provides a clock to the
8B/10B encoder and the read port of the byte serializer (if enabled) in the transmitter
channel PCS.
If the configured functional mode does not use the byte serializer, the low-speed
parallel clock from the CMU0 clock divider block clocks the read port of the transmitter
phase compensation FIFO in all four bonded channels. This low-speed parallel clock
is also driven directly on the coreclkout port as the FPGA fabric-transceiver interface
clock. You can use the coreclkout signal to clock transmitter data and control logic in
the FPGA fabric for all four bonded channels.
If the configured functional mode uses the byte serializer, the low-speed parallel clock
from the CMU0 clock divider is divided by two. This divide-by-two version of the
low-speed parallel clock provides a clock to the write port of the byte serializer and
the read port of the transmitter phase compensation FIFO in all four bonded channels.
It is also driven on the coreclkout port as the FPGA fabric-transceiver interface clock.
You can use the coreclkout signal to clock transmitter data and control logic in the
FPGA fabric for all four bonded channels.
In ×4 bonded channel configurations, the transmitter phase compensation FIFOs in all
four bonded channels share common read and write pointers and enable signals
generated in the CMU0 block channel of the transceiver block, ensuring equal
transmitter phase compensation FIFO latency across all four bonded channels,
resulting in low transmitter channel-to-channel skew.
Table 2–3
modes that have a fixed data rate.
Data Rate
(Gbps)
3.125
2.5
lists the transmitter datapath clock frequencies in ×4 bonded functional
5
Serial Clock
High-Speed
Frequency
1.5625
(GHz)
1.25
2.5
Parallel Clock
AN 610: Implementing CPRI and OBSAI Protocols in Altera
Low-Speed
Frequency
(MHz)
312.5
250
500
Chapter 2: Transceiver Clocking in Arria II Devices
FPGA Fabric-Transceiver Interface
Without Byte
Serializer
—
Transceiver Channel Datapath Clocking
—
—
December 2010 Altera Corporation
(2)
Clock Frequency
Serializer (MHz)
With Byte
156.25
125
250
Devices.