EP2AGX65DF29I5N Altera, EP2AGX65DF29I5N Datasheet - Page 289

• Manufacturer Part Number: EP2AGX65DF29I5N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29I5N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
Configuration Schemes
Configuration Schemes
Table 9–6. Configuration Schemes for Arria II GX Devices (Part 1 of 2)
December 2010 Altera Corporation
FPP
FPP with design security feature,
decompression, or both enabled
PS
User Mode
MSEL Pin Settings
Configuration Scheme
1
1
An optional INIT_DONE pin is available, which signals the end of initialization and the
start of user-mode with a low-to-high transition. The Enable INIT_DONE Output
option is available in the Quartus II software from the General tab of the Device and
Pin Options dialog box. If you use the INIT_DONE pin, it is high due to an external
10-kΩ pull-up resistor when nCONFIG is low and during the beginning of
configuration. After the option bit to enable INIT_DONE is programmed into the device
(during the first frame of configuration data), the INIT_DONE pin goes low. When
initialization is complete, the INIT_DONE pin is released and pulled high. When
initialization is complete, the device enters user mode. In user-mode, the user I/O
pins no longer have weak pull-up resistors and function as assigned in your design.
The following sections describe configuration schemes for Arria II devices.
Select the configuration scheme by driving the Arria II device MSEL pins either high or
low, as listed in
V
Altera recommends hardwiring the MSEL[] pins to V
MSEL[3..0] pins have 5-kΩ internal pull-down resistors that are always active.
During POR and during reconfiguration, the MSEL pins must be at LVTTL V
levels to be considered logic low and logic high, respectively.
To avoid problems with detecting an incorrect configuration scheme, hardwire the
MSEL[] pins to V
drive the MSEL[] pins by a microprocessor or another device.
For
MSEL[3..0] for Arria II GX devices and MSEL[2..0] for Arria II GZ devices as listed in
Table 9–6
CCPD
Figure 9–1 on page 9–12
and V
(2)
and
CCPGM
Table
Table 9–6
CCPD
power supplies for Arria II GX and GZ devices, respectively.
9–7, respectively.
MSEL3
/V
0
0
0
1
0
1
1
1
CCPGM
and
through
or GND without pull-up or pull-down resistors. Do not
Table
MSEL2
0
1
0
0
0
0
0
0
9–7. The MSEL input buffers are powered by the
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Figure 9–30 on page
MSEL1
0
1
0
0
1
0
1
1
MSEL0
CCPD
0
1
1
0
0
1
0
1
/V
9–66, MSEL[n..0] represents
POR Delay
CCPGM
Standard
Standard
Fast
Fast
Fast
Fast
Fast
Fast
or GND. The
Standard (V)
Configuration
3.3, 3.0, 2.5
3.3, 3.0, 2.5
3.3, 3.0, 2.5
3.3, 3.0, 2.5
Voltage
IL
1.8
1.8
1.8
1.8
and V
(1)
9–9
IH