EP2AGX65DF29I5N Altera, EP2AGX65DF29I5N Datasheet - Page 252

• Manufacturer Part Number: EP2AGX65DF29I5N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29I5N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

8–12
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Receiver Hardware Blocks
1
1
The Arria II PLL receives the external reference clock input (rx_inclock) and
generates eight different phases of the same clock. The DPA block chooses one of the
eight clock phases from the center/corner PLL and aligns to the incoming data to
maximize receiver skew margin. The synchronizer circuit is a 1-bit wide by 6-bit deep
FIFO buffer that compensates for any phase difference between the DPA block and the
deserializer. If necessary, the user-controlled data realignment circuitry inserts a single
bit of latency in the serial bit stream to align to the word boundary. The deserializer
converts the serial data to parallel data and sends the parallel data to the FPGA fabric.
The physical medium connecting the LVDS transmitter and the receiver channels may
introduce skew between the serial data and the source synchronous clock. The
instantaneous skew between each LVDS channel and the clock also varies with the
jitter on the data and clock signals, as seen by the receiver.
Only non-DPA mode requires manual skew adjustment.
Arria II devices support the following receiver modes to overcome skew between the
source-synchronous or reference clock and the received serial data:
■
■
■
Dedicated SERDES and DPA circuitry only exist on the right side of the device. Top
and bottom I/O banks only support non-DPA mode, in which the SERDES are
implemented in the core logic.
The differential receiver has the following hardware blocks:
■
■
■
■
DPA
The DPA block takes in high-speed serial data from the differential input buffer and
selects the optimal phase from one of the eight clock phases generated by the PLL to
sample the data. The eight phases of the clock are equally divided, giving a 45°
resolution. The maximum phase offset between the received data and the selected
phase is 1/8 unit interval (UI), which is the maximum quantization error of the DPA
block. The optimal clock phase selected by the DPA block (DPA_diffioclk) is also
used to write data into the FIFO buffer or to clock the SERDES for soft-CDR operation.
Non-DPA mode
DPA mode
Soft clock data recovery (CDR) mode
“DPA” on page 8–12
“Synchronizer” on page 8–13
“Data Realignment Block (Bit Slip)” on page 8–14
“Deserializer” on page 8–15
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II Devices
December 2010 Altera Corporation
Differential Receiver