EP2AGX65DF29I5N Altera, EP2AGX65DF29I5N Datasheet - Page 468

• Manufacturer Part Number: EP2AGX65DF29I5N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29I5N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

1–82
Arria II Device Handbook Volume 2: Transceivers
1
Word Aligner in XAUI Mode
The word aligner in XAUI functional mode is configured in automatic
synchronization state machine mode that is compliant to the PCS synchronization
state diagram specified in section 8 of the IEEE P802.3ae specification. The Quartus II
software automatically configures the synchronization state machine to indicate
synchronization when the receiver acquires four /K28.5/ comma code groups
without intermediate invalid code groups.
Receiver synchronization is indicated on the rx_syncstatus port of each channel. A
high on the rx_syncstatus port indicates that the lane is synchronized. The receiver
loses synchronization when it detects four invalid code groups separated by less than
four valid code groups, or when it is reset.
Deskew FIFO in XAUI Mode
The XAUI protocol requires the physical layer device to implement deskew circuitry
to align all four channels. The skew introduced in the physical medium and the
receiver channels can cause the /A/ code groups to be received misaligned with
respect to each other. To enable the deskew circuitry at the receiver to align the four
channels, the transmitter sends an /A/ (/K28.3/) code group simultaneously on all
four channels during an inter-packet gap (IPG). The deskew operation begins only
after link synchronization is achieved on all four channels as indicated by a high level
on the rx_syncstatus signal from the word aligner in each channel. Until the first
/A/ code group is received, the deskew FIFO read and write pointers in each channel
are not incremented. After the first /A/ code group is received, the write pointer
starts incrementing for each word received but the read pointer is frozen. If the /A/
code group is received on each of the four channels in 10 recovered clock cycles of
each other, the read pointer of all four deskew FIFOs is released simultaneously,
aligning all four channels.
The deskew FIFO operation in XAUI functional mode is compliant to the PCS deskew
state machine diagram specified in 8 of the IEEE P802.3ae specification.
Chapter 1: Transceiver Architecture in Arria II Devices
December 2010 Altera Corporation
Functional Modes