EP2AGX65DF29I5N Altera, EP2AGX65DF29I5N Datasheet - Page 199

• Manufacturer Part Number: EP2AGX65DF29I5N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29I5N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 7: External Memory Interfaces in Arria II Devices
Memory Interfaces Pin Support for Arria II Devices
Figure 7–2. External Memory Interface Datapath Overview for Arria II GZ Devices
Notes to
(1) You can bypass each register block.
(2) The blocks used for each memory interface may differ slightly. The shaded blocks are part of the Arria II GZ IOE.
(3) These signals may be bidirectional or unidirectional, depending on the memory standard. When bidirectional, the signal is active during both read
Memory Interfaces Pin Support for Arria II Devices
December 2010 Altera Corporation
Arria II GZ FPGA
and write operations.
Management
and Reset
Figure
Clock
7–2:
f
1
Half-Rate Resynchronization Clock
DQ Write Clock
Half-Rate Clock
DQS Write Clock
A typical memory interface requires data (D, Q, or DQ), data strobe (DQS/CQ and
DQSn/CQn), address, command, and clock pins. Some memory interfaces use data
mask (DM or BWSn) pins to enable write masking. This section describes how Arria II
devices support all these pins.
If you have more than one clock pair, you must place them in the same DQ group. For
example, if you have two clock pairs, you must place both of them in the same ×4
DQS group.
For more information about pin connections, refer to the
Connection
The DDR3, DDR2, DDR SDRAM, and RLDRAM II devices use CK and CK# signals to
capture the address and command signals. You can generate these signals to mimic
the write-data strobe with Arria II DDR I/O registers (DDIOs) to ensure that timing
relationships between the CK/CK# and DQS signals (t
DDR2, and DDR SDRAM devices) are met. The QDR II+/QDR II SRAM devices use
the same clock (K/K#) to capture the write data, address, and command signals.
DPRAM
Guidelines.
4n
4n
4
Postamble Enable
Postamble Clock
Half Data Rate
Input Registers
Output Registers
Output Registers
Half Data Rate
Half Data Rate
2n
Resynchronization Clock
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Synchronization
Postamble
Registers
Control
DLL
Circuit
2n
2
2n
DDR Input
(Note
DQS Enable
Registers
DQS Logic
DDR Output
DDR Output
and Output
and Output
Registers
Registers
Enable
Enable
Circuit
Block
DQSS
Arria II Device Family Pin
1),
, t
(2)
DSS
, and t
n
n
DSH
DQS (Read) (3)
DQ (Read) (3)
DQ (Write) (3)
DQS (Write) (3)
Memory
in DDR3,
7–3