EP2AGX65DF29I5N Altera, EP2AGX65DF29I5N Datasheet - Page 526

• Manufacturer Part Number: EP2AGX65DF29I5N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29I5N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

2–36
Figure 2–21. Sixteen Identical Channels Across Four Transceiver Blocks for Example 3
Arria II Device Handbook Volume 2: Transceivers
Transceiver Block GXBL3
Transceiver Block GXBL2
Transceiver Block GXBL1
Transceiver Block GXBL0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Limitations of the Quartus II Software-Selected Transmitter Phase Compensation FIFO Write
Clock
The Quartus II software uses a single tx_clkout signal to clock the transmitter phase
compensation FIFO write port of all identical channels within a transceiver block.
This usage results in one global or regional clock resource for each group of identical
channels within a transceiver block.
For identical channels located across transceiver blocks, the Quartus II software does
not use a single tx_clkout signal to clock the write port of the transmitter phase
compensation FIFOs for all channels. Instead, it uses one tx_clkout signal for each
group of identical channels per transceiver block, resulting in higher clock resource
utilization.
Consider 16 identical transmitter channels located across four transceiver blocks,
as shown in
in each transceiver block to clock the write port of the transmitter phase
compensation FIFO in all four channels of that transceiver block, resulting in four
clocks resources (global, regional, or both) being used, one for each transceiver
block.
Example 3: Sixteen Identical Channels Across Four Transceiver Blocks
Figure
tx_clkout[12]
tx_clkout[8]
tx_clkout[4]
tx_clkout[0]
2–21. The Quartus II software uses tx_clkout from Channel 0
tx_coreclk[15:12]
tx_coreclk[11:8]
tx_coreclk[7:4]
tx_coreclk[3:0]
FPGA Fabric
Chapter 2: Transceiver Clocking in Arria II Devices
FPGA Fabric-Transceiver Interface Clocking
Channel [15:12]
Channel [11:8]
Channel [3:0]
Channel [7:4]
and Control
and Control
and Control
and Control
TX Data
TX Data
TX Data
TX Data
Logic
Logic
Logic
Logic
December 2010 Altera Corporation