EP2AGX65DF29I5N Altera, EP2AGX65DF29I5N Datasheet - Page 145

• Manufacturer Part Number: EP2AGX65DF29I5N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29I5N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 5: Clock Networks and PLLs in Arria II Devices
PLLs in Arria II Devices
Figure 5–34. VCO Switchover Operating Frequency for Arria II Devices
December 2010 Altera Corporation
PLL Reconfiguration
DF vco
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PLLs use several divide counters and different VCO phase taps to perform frequency
synthesis and phase shifts. In Arria II PLLs, you can reconfigure both the counter
settings and phase-shift the PLL output clock in real time. You can also change the
charge pump and loop filter components, which dynamically affect the PLL
bandwidth. You can use these PLL components to update the output-clock frequency
and the PLL bandwidth and to phase shift in real time, without reconfiguring the
entire Arria II device.
The ability to reconfigure the PLL in real time is useful in applications that operate at
multiple frequencies. It is also useful in prototyping environments, allowing you to
sweep PLL output frequencies and adjust the output-clock phase dynamically. For
instance, a system generating test patterns is required to generate and transmit
patterns at 75 or 150 MHz, depending on the requirements of the device under test.
After a switchover event occurs, there may be a finite resynchronization period for
the PLL to lock onto a new clock. The exact amount of time it takes for the PLL to
relock depends on the PLL configuration.
If the phase relationship between the input clock to the PLL and the output clock
from the PLL is important in your design, assert areset for at least 10 ns after
performing a clock switchover.
To prevent clock glitches from propagating through your design during PLL
resynchronization or after areset is applied, use the clock enable feature of the
clock control block to disable the clock network. Wait for the locked signal to assert
and become stable before re-enabling the output clocks from the PLL at the clock
control block.
Figure 5–34
clock is lost and then increases as the VCO locks on to the backup clock.
Disable the system during clock switchover if it is not tolerant of frequency
variations during the PLL resynchronization period. You can use the clkbad[0]
and clkbad[1] status signals to turn off the PFD (PFDENA = 0) so the VCO
maintains its most recent frequency. You can also use the state machine to switch
over to the secondary clock. When the PFD is re-enabled, output clock-enable
signals (clkena) can disable the clock outputs during the switchover and
resynchronization period. After the lock indication is stable, the system can
re-enable the output clocks.
Primary Clock Stops Running
shows how the VCO frequency gradually decreases when the current
Switchover Occurs
Arria II Device Handbook Volume 1: Device Interfaces and Integration
VCO Tracks Secondary Clock
5–41