EP2AGX65DF29I5N Altera, EP2AGX65DF29I5N Datasheet - Page 34

• Manufacturer Part Number: EP2AGX65DF29I5N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29I5N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

2–6
Figure 2–6. Connection Details of the Arria II ALM
Arria II Device Handbook Volume 1: Device Interfaces and Integration
datac0
datac1
dataf0
datae0
dataa
datab
datae1
dataf1
Figure 2–6
One ALM contains two programmable registers. Each register has data, clock, clock
enable, synchronous and asynchronous clear, and synchronous load and clear inputs.
Global signals, general purpose I/O (GPIO) pins, or any internal logic can drive the
register ’s clock and clear-control signals. Either GPIO pins or internal logic can drive
the clock enable. For combinational functions, the register is bypassed and the output
of the LUT drives directly to the outputs of an ALM.
Each ALM has two sets of outputs that drive the local, row, and column routing
resources. The LUT, adder, or register output can drive the ALM outputs (refer to
Figure
or direct link routing connections, and one of these ALM outputs can also drive local
interconnect resources. The LUT or adder can drive one output while the register
drives another output.
3-INPUT
3-INPUT
3-INPUT
3-INPUT
4-INPUT
4-INPUT
2–6). For each set of output drivers, two ALM outputs can drive column, row,
LUT
LUT
LUT
LUT
LUT
LUT
shared_arith_out
shared_arith_in
shows a detailed view of all the connections in an ALM.
carry_in
carry_out
+
+
Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Arria II Devices
V CC
GND
clk[2:0]
syncload
sclr
aclr[1:0]
reg_chain_in
December 2010 Altera Corporation
D
D
CLR
CLR
reg_chain_out
Q
Q
Adaptive Logic Modules
local
interconnect
row, column
direct link routing
row, column
direct link routing
local
interconnect
row, column
direct link routing
row, column
direct link routing