EP2AGX65DF29I5N Altera, EP2AGX65DF29I5N Datasheet - Page 306

• Manufacturer Part Number: EP2AGX65DF29I5N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29I5N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

9–26
PS Configuration
Arria II Device Handbook Volume 1: Device Interfaces and Integration
PS Configuration Using a MAX II Device as an External Host
1
You can program PS configuration of Arria II devices using an intelligent host, such as
a MAX II device or microprocessor with flash memory, or a download cable. In the PS
scheme, an external host (a MAX II device, embedded processor, or host PC) controls
configuration. Configuration data is clocked into the target Arria II device using the
DATA0 pin at each rising edge of DCLK.
The Arria II decompression and design security features are available when
configuring your Arria II device using PS mode.
In this configuration scheme, you can use a MAX II device as an intelligent host that
controls the transfer of configuration data from a storage device, such as flash
memory, to the target Arria II device. You can store configuration data in .rbf, .hex, or
.ttf format.
Figure 9–10
and a MAX II device for single device configuration.
Figure 9–10. Single Device PS Configuration Using an External Host
Notes to
(1) Connect the pull-up resistor to a supply that provides an acceptable input signal for the Arria II device. For Arria II GX
(2) The MSEL pin settings vary for different configuration voltage standards and POR delays. To connect MSEL[3..0]for
(3) The nCEO pin can be left unconnected or used as a user I/O pin when it does not feed the nCE pin of the other device.
The Arria II device receives configuration data on the DATA0 pin and the clock is
received on the DCLK pin. Data is latched into the device on the rising edge of DCLK. If
you are using configuration data in .rbf, .hex, or .ttf format, you must send the LSB of
each data byte first. For example, if the .rbf contains the byte sequence
02 1B EE 01 FA, the serial bitstream you must transmit to the device is
0100-0000 1101-1000 0111-0111 1000-0000 0101-1111.
devices, use the V
V
system I/Os with V
an Arria II GX device, refer to
Table 9–7 on page
IH
specification of the I/O on both the device and the external host. Altera recommends powering the configuration
Figure
shows the configuration interface connections between an Arria II device
9–10:
(MAX II Device or
Microprocessor)
External Host
ADDR
CCIO
9–10.
CCIO
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
Memory
pin. For Arria II GZ devices, use the V
/V
CCPGM
DATA[0]
Table 9–6 on page
.
V
CCIO
10 k Ω
/ V
(1)
9–9. To connect MSEL[2..0] for an Arria II GZ device, refer to
CCPGM
10 k Ω
V
CCIO
CCPGM
GND
/ V
(1)
CCPGM
pin. V
CCIO
CONF_DONE
nSTATUS
nCE
DATA[0]
nCONFIG
DCLK
/V
Arria II Device
CCPGM
December 2010 Altera Corporation
must be high enough to meet the
MSEL[n..0]
nCEO
N.C.
(2)
PS Configuration
(3)