EP2AGX65DF29I5N Altera, EP2AGX65DF29I5N Datasheet - Page 577

• Manufacturer Part Number: EP2AGX65DF29I5N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29I5N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 4: Reset Control and Power Down in Arria II Devices
User Reset and Power-Down Signals
Table 4–1. Reset, Power-Down, and Status Signals for Arria II Devices (Part 2 of 2)
Table 4–2. Blocks Affected by Reset and Power-Down Signals for Arria II Devices
December 2010 Altera Corporation
busy
Notes to
(1) The tx_digitalreset and rx_digitalreset signals must be asserted until the clocks out of the transmitter PLL and receiver CDR are
(2) The refclk (refclk0 or refclk1) buffer is not powered down by this signal.
Transceiver Block
CMU PLLs
Transmitter Phase
Compensation FIFO
Byte Serializer
8B/10B Encoder
Serializer
Transmitter Buffer
Transmitter XAUI State
Machine
Receiver Buffer
Receiver CDR
Receiver Deserializer
Receiver Word Aligner
Receiver Deskew FIFO
Receiver Clock Rate
Compensation FIFO
Receiver 8B/10B Decoder
Receiver Byte Deserializer
Receiver Byte Ordering
Receiver Phase
Compensation FIFO
Receiver XAUI State
Machine
stabilized. Stable parallel clocks are essential for proper operation of the transmitter and receiver phase compensation FIFOs in the PCS.
Table
Blocks Affected by Reset and Power-Down Signals
Signal
4–1:
f
1
For more information, refer to
Arria II
If none of the channels is instantiated in a transceiver block, the Quartus
automatically powers down the entire transceiver block.
Table 4–2
rx_digitalreset
Indicates the status of the dynamic reconfiguration controller. The busy signal remains low for
the first reconfig_clk clock cycle after power up. It then is asserted from the second
reconfig_clk clock cycle. Assertion on this signal indicates that the offset cancellation
process is being executed on the receiver buffer as well as the receiver CDR. When this signal
is de-asserted, it indicates that the offset cancellation is complete.
Devices.
lists the blocks that are affected by specific reset and power-down signals.
v
v
v
v
v
v
v
v
rx_analogreset
v
AN 558: Implementing Dynamic Reconfiguration in
tx_digitalreset
Description
v
v
v
v
v
Arria II Device Handbook Volume 2: Transceivers
pll_powerdown
v
gxb_powerdown
®
II software
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
4–3