EP2AGX65DF29I5N Altera, EP2AGX65DF29I5N Datasheet - Page 41

• Manufacturer Part Number: EP2AGX65DF29I5N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29I5N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Arria II Devices
Adaptive Logic Modules
Figure 2–11. ALM in Shared Arithmetic Mode
December 2010 Altera Corporation
datae0
datae1
datab
dataa
datad
datac
Shared Arithmetic Mode
In shared arithmetic mode, the ALM can implement a 3-input add in an ALM. In this
mode, the ALM is configured with four 4-input LUTs. Each LUT either computes the
sum of three inputs or the carry of three inputs. The output of the carry computation
is fed to the next adder using a dedicated connection called the shared arithmetic
chain. This shared arithmetic chain can significantly improve the performance of an
adder tree by reducing the number of summation stages required to implement an
adder tree.
You can find adder trees in many different applications. For example, the summation
of the partial products in a logic-based multiplier can be implemented in a tree
structure. Another example is a correlator function that can use a large adder tree to
sum filtered data samples in a given time frame to recover or de-spread data that was
transmitted using spread-spectrum technology.
Figure 2–11
4-Input
4-Input
4-Input
4-Input
LUT
LUT
LUT
LUT
shared_arith_out
shows the ALM using this feature.
shared_arith_in
carry_out
carry_in
Arria II Device Handbook Volume 1: Device Interfaces and Integration
labclk
D
D
reg0
reg1
Q
Q
To general or
To general or
To general or
To general or
local routing
local routing
local routing
local routing
2–13