EP2AGX65DF29I5N Altera, EP2AGX65DF29I5N Datasheet - Page 57

• Manufacturer Part Number: EP2AGX65DF29I5N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29I5N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 3: Memory Blocks in Arria II Devices
Memory Modes
Figure 3–10. Timing Waveform for Read-Write Operations for M9K and M144K Blocks (Single-Port Mode)
December 2010 Altera Corporation
q_a (asynch)
address_a
data_a
wrena
rdena
clk_a
During a write operation, the RAM output behavior is configurable. If you use the
read-enable signal and perform a write operation with the read enable deactivated,
the RAM outputs retain the values they held during the most recent active read
enable. If you activate read enable during a write operation, or if you do not use the
read-enable signal at all, the RAM outputs show the “new data” being written, the
“old data” at that address, or a “don’t care” value.
Table 3–4
mode.
Table 3–4. Port Width Configurations for MLABs, M9K, and M144K Blocks (Single-Port Mode)
Figure 3–10
mode with unregistered outputs for M9K and M144K blocks. Registering the M9K
and M144K block outputs delay the q output by one clock cycle.
lists the possible port width configurations for memory blocks in single-port
64 × 10
32 × 16
32 × 18
32 × 20
MLABs
shows timing waveforms for read and write operations in single-port
A
64 × 8
64 × 9
a0(old data)
B
a0
A
Port Width Configurations
C
Arria II Device Handbook Volume 1: Device Interfaces and Integration
B
M9K Blocks
512 × 16
512 × 18
256 × 32
256 × 36
8K × 1
4K × 2
2K × 4
1K × 8
1K × 9
D
a1(old data)
a1
E
D
F
M144K Blocks
E
16K × 8
16K × 9
8K × 16
8K × 18
4K × 32
4K × 36
2K × 64
2K × 72
3–11