EP2AGX65DF29I5N Altera, EP2AGX65DF29I5N Datasheet - Page 167

• Manufacturer Part Number: EP2AGX65DF29I5N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29I5N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 6: I/O Features in Arria II Devices
I/O Banks
Table 6–5. Pin Migration Across Densities in Arria II GX Devices
December 2010 Altera Corporation
Package
358-pin
Flip Chip
UBGA
572-pin
Flip Chip
FBGA
780-pin
Flip Chip
FBGA
1152-pin
Flip Chip
FBGA
Note to
(1) Each transceiver channel consists of two transmit (Tx) pins, two receive (Rx) pins and a transceiver clock pin.
Table
6–5:
Pin Type
I/O
Clock
XCVR
channel
I/O
Clock
XCVR
channel
I/O
Clock
XCVR
channel
I/O
Clock
XCVR
channel
In the Arria II devices, the maximum number of I/O banks per side excluding the
configuration banks is either four or six, depending on the device density. All Arria II
devices support migration across device densities and packages. When migrating
between devices with a different number of I/O banks per side, it is the "B" bank that
is removed or inserted. For example, when moving from a 12-bank device to an
8-bank device, the banks that are dropped are "B" banks, namely: 3B, 5B, 6B, and 8B.
Similarly, when moving from an 8-bank device to a 12-bank device, the banks that are
added are "B" banks, namely: 3B, 5B, 6B, and 8B.
During migration from a smaller device to a larger device, the bank size increases or
remains the same but never decreases.
across device densities and packages.
Table 6–6. Pin Migration Across Densities in Arria II GZ Devices
780-pin Flip Chip
FBGA
EP2AGX45
Package
144
240
352
12
12
12
—
—
—
4
8
8
EP2AGX65
144
240
352
12
12
12
—
—
—
4
8
8
I/O
Clock
XVCR channel
Pin Type
EP2AGX95
248
360
440
—
—
—
12
12
12
12
12
8
Device
Arria II Device Handbook Volume 1: Device Interfaces and Integration
(Note 1)
EP2AGX125 EP2AGX190 EP2AGX260
Table 6–5
EP2AGZ225
248
360
440
—
—
—
12
12
12
12
12
8
—
—
—
and
Table 6–6
360
600
—
—
—
—
—
—
12
12
12
16
EP2AGZ300
(Note 1)
Device
280
16
1
list the pin migration
(Part 1 of 2)
360
600
—
—
—
—
—
—
12
12
12
16
EP2AGZ350
280
16
1
6–9