EP2AGX65DF29I5N Altera, EP2AGX65DF29I5N Datasheet - Page 445

• Manufacturer Part Number: EP2AGX65DF29I5N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29I5N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 1: Transceiver Architecture in Arria II Devices
Functional Modes
Figure 1–57. GIGE Functional Mode
Notes to
(1) The word aligner uses automatic synchronization state machine mode (7-bit comma, 10-Bit /K28.5/).
(2) High-speed serial clock is running at 625 MHz.
(3) These clocks are running at 125 MHz.
December 2010 Altera Corporation
(3)
Fabric
FPGA
Figure
1–57:
1
8-Bit Interface @ 125 MHz
Figure 1–57
mode.
Idle Ordered-Set Generation in GIGE Mode
The IEEE 802.3 specification requires the GIGE PHY to transmit idle ordered sets (/I/)
continuously and repetitively whenever the GMII is idle. This ensures that the
receiver maintains bit and word synchronization whenever there is no active data to
be transmitted.
In GIGE functional mode, any /Dx.y/ following a /K28.5/ comma is replaced by the
transmitter with either a /D5.6/ (/I1/ ordered set) or a /D16.2/ (/I2/ ordered set),
depending on the current running disparity. The exception is when the data following
the /K28.5/ is /D21.5/ (/C1/ ordered set) or /D2.2/ (/C2/) ordered set. If the
running disparity before the /K28.5/ is positive, an /I1/ ordered set is generated. If
the running disparity is negative, an /I2/ ordered set is generated. The disparity at
the end of an /I1/ is the opposite of that at the beginning of the /I1/. The disparity at
the end of an /I2/ is the same as the beginning running disparity (right before the idle
code). This ensures a negative running disparity at the end of an idle ordered set. A
/Kx.y/ following a /K28.5/ is not replaced.
/D14.3/, /D24.0/, and /D15.8/ are replaced by /D5.6/ or /D16.2/ (for /I1/
and /I2/ ordered sets). /D21.5/ (part of the /C1/ order set) is not replaced.
(3)
(3)
(3)
tx_clkout[0]
Compensation
wrclk
shows the transceiver datapath when configured in GIGE functional
TX Phase
FIFO
rdclk
/2
wrclk
Byte Serializer
/2
Receiver Channel PCS
Transmitter Channel PCS
rdclk
8B/10B Encoder
Low-Speed Parallel Clock (3)
Low-Speed Parallel Clock (3)
Parallel Recovery Clock (3)
Arria II Device Handbook Volume 2: Transceivers
Interface
10-Bit
Transmitter Channel
Receiver Channel
Local Clock
Divider
PMA
PMA
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