EP2AGX65DF29I5N Altera, EP2AGX65DF29I5N Datasheet - Page 432

• Manufacturer Part Number: EP2AGX65DF29I5N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29I5N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

1–46
Table 1–14. RX Phase Compensation FIFO Modes for Arria II Devices
Arria II Device Handbook Volume 2: Transceivers
Low Latency
High-Latency
Register
Note to
(1) Pending characterization.
Table
Mode
1–14:
RX Phase Compensation FIFO
The RX phase compensation FIFO in each channel ensures reliable transfer of data
and status signals between the receiver channel and the FPGA fabric. The RX phase
compensation FIFO compensates for the phase difference between the parallel
receiver PCS clock (FIFO write clock) and the FPGA fabric clock (FIFO read clock).
Table 1–14
automatically sets the mode that applies to a particular functional mode.
Figure 1–46
and read clock to the FIFO are at half-rate if the byte serializer is used in the
configuration.
Figure 1–46. RX Phase Compensation FIFO Block Diagram
Notes to
(1) The tx_clkout clock is from the transmitter channel clock divider and is used in non-bonded configurations with
(2) The rx_clkout clock is from the receiver channel CDR and is used in non-bonded configurations that does not use
(3) The coreclkout clock is from the CMU0 block of the associated transceiver block or the master transceiver block for
(4) Use this clock for the FIFO read clock if you instantiate the rx_coreclk port in the ALTGX MegaWizard Plug-In
(5) The rx_phase_comp_fifo_error is optional and available in all functional modes. This signal is asserted high to
into the LSByte position after a rising edge on the rx_enabyteord signal. If the byte
ordering blocks find the first data byte that matches the programmed byte
ordering pattern in the LSByte position of the byte-deserialized data, it considers
the data to be byte ordered and does not insert any PAD byte. In either case, the
byte ordering block asserts the rx_byteorderalignstatus signal.
4-words deep
8-words deep
the rate match FIFO.
the rate match FIFO.
×4 bonded or ×8 bonded channel configurations, respectively.
Manager, regardless of the channel configurations. Otherwise, use the same clock used for the write clock for the
read clock.
indicate an overflow or underflow condition.
FIFO Depth
Figure
coreclkout (3)
—
tx_clkout (1)
rx_clkout (2)
lists the RX phase compensation FIFO modes. The Quartus II software
shows the RX phase compensation FIFO block diagram. The write clock
1–46:
rx_coreclk (4)
2-to-3 parallel clock cycles
4-to-5 parallel clock cycles
Latency Through FIFO
Data from the Byte
Ordering, Byte
Deserialization,
or 8B/10B Decoder
1
Write Clock
Compensation
(1)
(1)
Phase
FIFO
Chapter 1: Transceiver Architecture in Arria II Devices
RX
Read Clock
All functional modes except PCIe and
Applicable Functional Modes
rx_dataout to the FPGA fabric
rx_phase_comp_fifo_error (5)
Deterministic Latency
Deterministic Latency
December 2010 Altera Corporation
PCIe
Receiver Channel Datapath