EP2AGX65DF29I5N Altera, EP2AGX65DF29I5N Datasheet - Page 82

• Manufacturer Part Number: EP2AGX65DF29I5N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29I5N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

4–10
Table 4–3. Input Register Modes for Arria II Devices
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Parallel input
Shift register input
Loopback input
Notes to
(1) The multiplier operand input word lengths are statically configured at compile time.
(2) Available only on the A-operand.
(3) Only one loopback input is allowed per half block. For details, refer to
Register Input Mode
Table
4–3:
(3)
(2)
All DSP block registers are triggered by the positive edge of the clock signal and are
cleared after power up. Each multiplier operand can feed an input register or feed
directly to the multiplier, bypassing the input registers. The clock[3..0], ena[3..0],
and aclr[3..0]DSP block signals control the input registers in the DSP block.
Every DSP block has nine 18-bit data input register banks per half-DSP block. Every
half-DSP block has the option to use the eight data register banks as inputs to the four
multipliers. The special ninth register bank is a delay register required by modes that
use both the cascade and chainout features of the DSP block to balance the latency
requirements when using the chained cascade feature. A feature of the input register
bank is to support a tap delay line. Therefore, you can drive the top leg of the
multiplier input (A) from general routing or from the cascade chain, as shown in
Figure
At compile time, you must select the incoming data for multiplier input (A) from
either general routing or from the cascade chain. In cascade mode, the dedicated shift
outputs from one multiplier block directly feeds input registers of the adjacent
multiplier below it (in the same half-DSP block) or the first multiplier in the next
half-DSP block, to form an 8-tap shift register chain per DSP block. The DSP block can
increase the length of the shift register chain by cascading to the lower DSP blocks.
The dedicated shift register chain spans a single column, but you can implement
longer shift register chains requiring multiple columns with the regular FPGA routing
resources.
Shift registers are useful in DSP functions such as FIR filters. When implementing an
18 × 18 or smaller width multiplier, you do not require external logic to create the shift
register chain because the input shift registers are internal to the DSP block. This
implementation significantly reduces the logical element (LE) resources required,
avoids routing congestion, and results in predictable timing.
The first multiplier in every half-DSP block (top- and bottom-half) has a multiplexer
for the first multiplier B-input (lower-leg input) register to select between general
routing and loopback, as shown in
most significant 18-bit registered outputs are connected as feedback to the multiplier
input of the first top multiplier in each half-DSP block. Loopback modes are used by
recursive filters where the previous output is required to compute the current output.
Loopback mode is described in detail in
page
Table 4–3
(1)
4–20.
4–6.
lists the summary of input register modes for the DSP block.
9 × 9
v
—
—
12 × 12
v
—
—
Figure 4–14 on page
Figure 4–5 on page
“Two-Multiplier Adder Sum Mode” on
18 × 18
v
v
v
4–21.
4–8. In loopback mode, the
Chapter 4: DSP Blocks in Arria II Devices
December 2010 Altera Corporation
36 × 36
DSP Block Resource Descriptions
v
—
—
Double
v
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