EP2AGX65DF29I5N Altera, EP2AGX65DF29I5N Datasheet - Page 371

• Manufacturer Part Number: EP2AGX65DF29I5N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29I5N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 12: Power Management in Arria II Devices
Power-On Reset Circuitry
Power-On Reset Circuitry
December 2010 Altera Corporation
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The Arria II power-on reset (POR) circuitry generates a POR signal to keep the device
in the reset state until the power supply’s voltage levels have stabilized during
power-up. The POR circuitry monitors V
supplies for I/O banks 3C and 8C in Arria II GX devices, where the configuration pins
are located. The POR circuitry tri-states all user I/O pins until the power supplies
reach the recommended operating levels. These power supplies are required to
monotonically reach their full-rail values without plateaus and within the maximum
power supply ramp time (t
the power supplies reach their full-rail values to release the device from the reset
state.
The POR circuitry monitors V
Arria II GZ devices. The POR circuitry keeps the Arria II GZ devices in reset state
until the power supply outputs are within operating range (provided that the V
powers up fully before V
POR circuitry is important to ensure that all the circuits in the Arria II device are at
certain known states during power up. You can select the POR signal pulse width
between fast POR time or standard POR time using the MSEL pin settings. For fast
POR time, the POR signal pulse width is set to 4 ms for the power supplies to ramp up
to full rail. For standard POR time, the POR signal pulse width is set to 100 ms for the
power supplies to ramp up to full rail. In both cases, you can extend the POR time
with an external component to assert the nSTATUS pin low.
For more information about the POR specification, refer to the
Arria II Devices
For more information about MSEL pin settings, refer to the
Security, and Remote System Upgrades in Arria II Devices
chapter.
CCAUX
RAMP
CC
).
.). The POR circuitry de-asserts the POR signal after
, V
CCAUX
Arria II Device Handbook Volume 1: Device Interfaces and Integration
, V
CC
, V
CCCB
CCA_PLL
, V
CCPGM
, V
chapter.
CCCB
, and V
Configuration, Design
, V
Device Datasheet for
CCPD
CCPD
, and V
supplies in
CCIO
CC
12–3