EP2AGX65DF29I5N Altera, EP2AGX65DF29I5N Datasheet - Page 396

• Manufacturer Part Number: EP2AGX65DF29I5N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29I5N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

1–10
Figure 1–8. CMU0 Clock Divider Block
Notes to
(1) The Quartus II software automatically selects all the divider settings based on the input clock frequency, data rate, deserialization width, and
(2) The high-speed serial clock is available to all the transmitter channels in the transceiver block. In a ×8 configuration, only the CMU0 clock divider
(3) If the byte serializer block is enabled in bonded channel modes, the coreclkout clock output is half the frequency of the low-speed parallel clock.
Transmitter Channel Local Clock Divider Block
Arria II Device Handbook Volume 2: Transceivers
CMU0 High-Speed Clock Output
CMU1 High-Speed Clock Output
channel width settings.
of the master transceiver block provides the high-speed serial clock to all eight channels.
Otherwise, the coreclkout clock output is the same frequency as the low-speed parallel clock.
Figure
CMU0 Clock Divider
1–8:
f
The clock divider is only available only in the CMU0 block and is used in bonded
functional modes.
Figure 1–8
Each transmitter channel contains a local clock divider block used automatically by
the Quartus II software for non-bonded functional modes (for example, ×1 PCIe,
GIGE, SONET/SDH, and SDI mode). This block allows each transmitter channel to
run at /1, /2, or /4 of the CMU PLL output data rate.
Figure 1–9
Figure 1–9. Transmitter Local Clock Divider Block
For more information about transceiver channel local clock divider block clocking,
refer to the “Transceiver Channel Datapath Clocking” section in the
Clocking in Arria II Devices
CMU0 PLL High-Speed Clock
CMU1 PLL High-Speed Clock
shows a diagram of the CMU0 clock divider block.
shows the transmitter local clock divider block.
/N (1, 2, 4)
(Note 1)
CMU0 Clock Divider Block
chapter.
/S (4, 5, 8, 10)
1, 2, or 4
n
Chapter 1: Transceiver Architecture in Arria II Devices
4, 5, 8, or 10
/2
Transmitter Channel Local Clock Divider Block
December 2010 Altera Corporation
High-Speed Serial Clock (2)
coreclkout to FPGA Fabric (3)
Low-Speed Parallel Clock
for Transmitter Channel PCS
High-Speed Serial Clock
for the Serializer
Low-Speed Parallel Clock
for the Transmitter PCS Blocks
tx_clkout for the
FPGA Fabric
Transceiver