PIC12F1840-I/P Microchip Technology, PIC12F1840-I/P Datasheet - Page 100

• Manufacturer Part Number: PIC12F1840-I/P
• Description: 7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core 8 PDI
• Manufacturer: Microchip Technology

Specifications of PIC12F1840-I/P

• Processor Series: PIC12F
• Core: PIC
• Program Memory Type: Flash
• Program Memory Size: 7 KB
• Data Ram Size: 256 B
• Interface Type: MI2C, SPI, EUSART
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Package / Case: PDIP-8
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC12(L)F1840
11.3
It is important to understand the Flash program mem-
ory structure for erase and programming operations.
Flash Program memory is arranged in rows. A row con-
sists of a fixed number of 14-bit program memory
words. A row is the minimum block size that can be
erased by user software.
Flash program memory may only be written or erased
if the destination address is in a segment of memory
that is not write-protected, as defined in bits WRT<1:0>
of Configuration Word 2.
After a row has been erased, the user can reprogram
all or a portion of this row. Data to be written into the
program memory row is written to 14-bit wide data write
latches. These write latches are not directly accessible
to the user, but may be loaded via sequential writes to
the EEDATH:EEDATL register pair.
The number of data write latches may not be equivalent
to the number of row locations. During programming,
user software may need to fill the set of write latches
and initiate a programming operation multiple times in
order to fully reprogram an erased row. For example, a
device with a row size of 32 words and eight write
latches will need to load the write latches with data and
initiate a programming operation four times.
The size of a program memory row and the number of
program memory write latches may vary by device.
See
TABLE 11-1:
DS41441B-page 100
PIC12(L)F1840
Note:
Table 11-1
Device
Flash Program Memory Overview
If the user wants to modify only a portion
of a previously programmed row, then the
contents of the entire row must be read
and saved in RAM prior to the erase.
for details.
FLASH MEMORY
ORGANIZATION BY DEVICE
EEADRL<4:0>
Erase Block
(Row) Size/
Boundary
32 words,
= 00000
Write Latches/
EEADRL<4:0>
Number of
Boundary
32 words,
= 00000
Preliminary
11.3.1
To read a program memory location, the user must:
1.
2.
3.
4.
Once the read control bit is set, the program memory
Flash controller will use the second instruction cycle to
read the data. This causes the second instruction
immediately following the “BSF EECON1,RD” instruction
to be ignored. The data is available in the very next cycle,
in the EEDATH:EEDATL register pair; therefore, it can
be read as two bytes in the following instructions.
EEDATH:EEDATL register pair will hold this value until
another read or until it is written to by the user.
Note 1: The two instructions following a program
Write the Least and Most Significant address
bits to the EEADRH:EEADRL register pair.
Clear the CFGS bit of the EECON1 register.
Set the EEPGD control bit of the EECON1
register.
Then, set control bit RD of the EECON1 register.
2: Flash program memory can be read
READING THE FLASH PROGRAM
MEMORY
memory read are required to be NOPs.
This prevents the user from executing a
two-cycle
instruction after the RD bit is set.
regardless of the setting of the CP bit.
 2011 Microchip Technology Inc.
instruction
on
the
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