PIC12F1840-I/P Microchip Technology, PIC12F1840-I/P Datasheet - Page 75

7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core 8 PDI

PIC12F1840-I/P

Manufacturer Part Number
PIC12F1840-I/P
Description
7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core 8 PDI
Manufacturer
Microchip Technology
Datasheet

Specifications of PIC12F1840-I/P

Processor Series
PIC12F
Core
PIC
Program Memory Type
Flash
Program Memory Size
7 KB
Data Ram Size
256 B
Interface Type
MI2C, SPI, EUSART
Number Of Timers
3
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Package / Case
PDIP-8
Development Tools By Supplier
MPLAB IDE Software
Minimum Operating Temperature
- 40 C
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC12F1840-I/P
Manufacturer:
MICROCHIP
Quantity:
200
7.11
The Power Control (PCON) register contains flag bits
to differentiate between a:
• Power-on Reset (POR)
• Brown-out Reset (BOR)
• Reset Instruction Reset (RI)
• Stack Overflow Reset (STKOVF)
• Stack Underflow Reset (STKUNF)
• MCLR Reset (RMCLR)
The PCON register bits are shown in
REGISTER 7-2:
 2011 Microchip Technology Inc.
bit 7
Legend:
HC = Bit is cleared by hardware
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6
bit 5-4
bit 3
bit 2
bit 1
bit 0
R/W/HS-0/q
STKOVF
Power Control (PCON) Register
STKOVF: Stack Overflow Flag bit
1 = A Stack Overflow occurred
0 = A Stack Overflow has not occurred or set to ‘0’ by firmware
STKUNF: Stack Underflow Flag bit
1 = A Stack Underflow occurred
0 = A Stack Underflow has not occurred or set to ‘0’ by firmware
Unimplemented: Read as ‘0’
RMCLR: MCLR Reset Flag bit
1 = A MCLR Reset has not occurred or set to ‘1’ by firmware
0 = A MCLR Reset has occurred (set to ‘0’ in hardware when a MCLR Reset occurs)
RI: RESET Instruction Flag bit
1 = A RESET instruction has not been executed or set to ‘1’ by firmware
0 = A RESET instruction has been executed (set to ‘0’ in hardware upon executing a RESET instruction)
POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset
R/W/HS-0/q
STKUNF
occurs)
PCON: POWER CONTROL REGISTER
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U-0
Register
7-2.
U-0
Preliminary
U = Unimplemented bit, read as ‘0’
-m/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
R/W/HC-1/q
HS = Bit is set by hardware
RMCLR
R/W/HC-1/q
PIC12(L)F1840
RI
R/W/HC-q/u
POR
DS41441B-page 75
R/W/HC-q/u
BOR
bit 0

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