PIC12F1840-I/P Microchip Technology, PIC12F1840-I/P Datasheet - Page 203

• Manufacturer Part Number: PIC12F1840-I/P
• Description: 7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core 8 PDI
• Manufacturer: Microchip Technology

Specifications of PIC12F1840-I/P

• Processor Series: PIC12F
• Core: PIC
• Program Memory Type: Flash
• Program Memory Size: 7 KB
• Data Ram Size: 256 B
• Interface Type: MI2C, SPI, EUSART
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Package / Case: PDIP-8
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

24.4.4
In Half-Bridge applications where all power switches
are modulated at the PWM frequency, the power
switches normally require more time to turn off than to
turn on. If both the upper and lower power switches are
switched at the same time (one turned on, and the
other turned off), both switches may be on for a short
period of time until one switch completely turns off.
During this brief interval, a very high current (shoot-
through current) will flow through both power switches,
shorting the bridge supply. To avoid this potentially
destructive shoot-through current from flowing during
switching, turning on either of the power switches is
normally delayed to allow the other switch to
completely turn off.
In Half-Bridge mode, a digitally programmable dead-
band delay is available to avoid shoot-through current
from destroying the bridge power switches. The delay
occurs at the signal transition from the non-active state
to the active state. See
The lower seven bits of the associated PWM1CON
register
of microcontroller instruction cycles (T
FIGURE 24-13:
 2011 Microchip Technology Inc.
Standard Half-Bridge Circuit (“Push-Pull”)
(Register
PROGRAMMABLE DEAD-BAND
DELAY MODE
24-3) sets the delay period in terms
EXAMPLE OF HALF-BRIDGE APPLICATIONS
Figure 24-12
CY
for illustration.
or 4 T
P1A
P1B
OSC
).
Preliminary
FET
Driver
FET
Driver
FIGURE 24-12:
P1A
P1B
td = Dead-Band Delay
Note 1: At this time, the TMR2 register is equal to the
(2)
(2)
V+
V-
2: Output signals are shown as active-high.
(1)
td
Pulse Width
PR2 register.
Load
Period
PIC12(L)F1840
td
EXAMPLE OF HALF-
BRIDGE PWM OUTPUT
+
V
-
+
V
-
(1)
DS41441B-page 203
Period
(1)