PIC12F1840-I/P Microchip Technology, PIC12F1840-I/P Datasheet - Page 85

• Manufacturer Part Number: PIC12F1840-I/P
• Description: 7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core 8 PDI
• Manufacturer: Microchip Technology

Specifications of PIC12F1840-I/P

• Processor Series: PIC12F
• Core: PIC
• Program Memory Type: Flash
• Program Memory Size: 7 KB
• Data Ram Size: 256 B
• Interface Type: MI2C, SPI, EUSART
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Package / Case: PDIP-8
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

8.5.3
The PIE2 register contains the interrupt enable bits, as
shown in
REGISTER 8-3:
 2011 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
R/W-0/0
OSFIE
Register
PIE2 REGISTER
OSFIE: Oscillator Fail Interrupt Enable bit
1 = Enables the Oscillator Fail interrupt
0 = Disables the Oscillator Fail interrupt
Unimplemented: Read as ‘0’
C1IE: Comparator C1 Interrupt Enable bit
1 = Enables the Comparator C1 interrupt
0 = Disables the Comparator C1 interrupt
EEIE: EEPROM Write Completion Interrupt Enable bit
1 = Enables the EEPROM Write Completion interrupt
0 = Disables the EEPROM Write Completion interrupt
BCL1IE: MSSP Bus Collision Interrupt Enable bit
1 = Enables the MSSP Bus Collision Interrupt
0 = Disables the MSSP Bus Collision Interrupt
Unimplemented: Read as ‘0’
8-3.
U-0
—
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
R/W-0/0
C1IE
R/W-0/0
EEIE
Preliminary
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
R/W-0/0
BCL1IE
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
U-0
PIC12(L)F1840
—
U-0
—
DS41441B-page 85
U-0
—
bit 0