PIC12F1840-I/P Microchip Technology, PIC12F1840-I/P Datasheet - Page 117

• Manufacturer Part Number: PIC12F1840-I/P
• Description: 7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core 8 PDI
• Manufacturer: Microchip Technology

Specifications of PIC12F1840-I/P

• Processor Series: PIC12F
• Core: PIC
• Program Memory Type: Flash
• Program Memory Size: 7 KB
• Data Ram Size: 256 B
• Interface Type: MI2C, SPI, EUSART
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Package / Case: PDIP-8
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

REGISTER 12-6:
TABLE 12-1:
TABLE 12-2:
 2011 Microchip Technology Inc.
CONFIG1
Legend:
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7-6
bit 5-0
Note 1:
ANSELA
APFCON
LATA
OPTION_REG
PORTA
TRISA
WPUA
Legend:
Name
Name
U-0
—
2:
— = unimplemented location, read as ‘0’. Shaded cells are not used by PORTA.
Global WPUEN bit of the OPTION register must be cleared for individual pull-ups to be enabled.
The weak pull-up device is automatically disabled if the pin is in configured as an output.
x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.
13:8
Bits
7:0
RXDTSEL
Unimplemented: Read as ‘0’
WPUA<5:0>: Weak Pull-up Register bits
1 = Pull-up enabled
0 = Pull-up disabled
WPUEN
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
SUMMARY OF CONFIGURATION WORD WITH PORTA
Bit 7
—
—
—
—
—
Bit -/7
U-0
CP
—
—
WPUA: WEAK PULL-UP PORTA REGISTER
SDOSEL
INTEDG
Bit 6
MCLRE
Bit -/6
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
—
—
—
—
—
—
R/W-1/1
WPUA5
TMR0CS
TRISA5
WPUA5
SSSEL
LATA5
PWRTE
Bit 5
Bit 13/5
FCMEN
RA5
—
R/W-1/1
WPUA4
Preliminary
TMR0SE
TRISA4
WPUA4
ANSA4
LATA4
Bit 4
RA4
Bit 12/4
---
IESO
WDTE<1:0>
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
R/W-1/1
WPUA3
T1GSEL
TRISA3
WPUA3
CLKOUTEN
Bit 3
PSA
RA3
Bit 11/3
—
—
TXCKSEL
TRISA2
WPUA2
ANSA2
LATA2
Bit 2
RA2
Bit 10/2
R/W-1/1
WPUA2
PIC12(L)F1840
BOREN<1:0>
PS<2:0>
FOSC<2:0>
P1BSEL
TRISA1
WPUA1
ANSA1
LATA1
Bit 1
RA1
Bit 9/1
R/W-1/1
WPUA1
CCP1SEL
TRISA0
WPUA0
ANSA0
LATA0
DS41441B-page 117
Bit 0
RA0
Bit 8/0
CPD
R/W-1/1
WPUA0
Register
on Page
Register
on Page
161
116
112
116
115
115
117
42
bit 0