PIC12F1840-I/P Microchip Technology, PIC12F1840-I/P Datasheet - Page 46

7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core 8 PDI

PIC12F1840-I/P

Manufacturer Part Number
PIC12F1840-I/P
Description
7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core 8 PDI
Manufacturer
Microchip Technology
Datasheet

Specifications of PIC12F1840-I/P

Processor Series
PIC12F
Core
PIC
Program Memory Type
Flash
Program Memory Size
7 KB
Data Ram Size
256 B
Interface Type
MI2C, SPI, EUSART
Number Of Timers
3
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Package / Case
PDIP-8
Development Tools By Supplier
MPLAB IDE Software
Minimum Operating Temperature
- 40 C
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC12F1840-I/P
Manufacturer:
MICROCHIP
Quantity:
200
PIC12(L)F1840
4.5
The memory location 8006h is where the Device ID and
Revision ID are stored. The upper nine bits hold the
Device ID. The lower five bits hold the Revision ID. See
Section 11.5 “User ID, Device ID and Configuration
Word Access” for more information on accessing
these memory locations.
Development tools, such as device programmers and
debuggers, may be used to read the Device ID and
Revision ID.
REGISTER 4-3:
DS41441B-page 46
bit 13
bit 6
Legend:
R = Readable bit
-n = Value at POR
bit 13-5
bit 4-0
Note 1:
DEV8
DEV1
R
R
Device ID and Revision ID
This location cannot be written.
DEV<8:0>: Device ID bits
011011100 = PIC12F1840
011011110 = PIC12LF1840
REV<4:0>: Revision ID bits
These bits are used to identify the revision.
DEVICEID: DEVICE ID REGISTER
DEV7
DEV0
R
R
W = Writable bit
‘1’ = Bit is set
DEV6
REV4
R
R
Preliminary
DEV5
REV3
R
R
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
DEV4
REV2
R
R
 2011 Microchip Technology Inc.
DEV3
REV1
R
R
DEV2
REV0
R
R
bit 7
bit 0

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