PIC12F1840-I/P Microchip Technology, PIC12F1840-I/P Datasheet - Page 161

• Manufacturer Part Number: PIC12F1840-I/P
• Description: 7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core 8 PDI
• Manufacturer: Microchip Technology

Specifications of PIC12F1840-I/P

• Processor Series: PIC12F
• Core: PIC
• Program Memory Type: Flash
• Program Memory Size: 7 KB
• Data Ram Size: 256 B
• Interface Type: MI2C, SPI, EUSART
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Package / Case: PDIP-8
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

REGISTER 20-1:
TABLE 20-1:
 2011 Microchip Technology Inc.
CPSCON0
INTCON
OPTION_REG WPUEN
TMR0
TRISA
Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by the Timer0 module.
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
R/W-1/1
WPUEN
Name
*
Page provides register information.
Timer0 Module Register
WPUEN: Weak Pull-up Enable bit
1 = All weak pull-ups are disabled (except MCLR, if it is enabled)
0 = Weak pull-ups are enabled by individual WPUA latch values
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RA2/INT pin
0 = Interrupt on falling edge of RA2/INT pin
TMR0CS: Timer0 Clock Source Select bit
1 = Transition on RA2/T0CKI pin
0 = Internal instruction cycle clock (F
TMR0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on RA2/T0CKI pin
0 = Increment on low-to-high transition on RA2/T0CKI pin
PSA: Prescaler Assignment bit
1 = Prescaler is not assigned to the Timer0 module
0 = Prescaler is assigned to the Timer0 module
PS<2:0>: Prescaler Rate Select bits
CPSON
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0
INTEDG
Bit 7
R/W-1/1
GIE
—
OPTION_REG: OPTION REGISTER
Bit Value
INTEDG TMR0CS TMR0SE
CPSRM
000
001
010
011
100
101
110
111
PEIE
Bit 6
—
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
TMR0CS
R/W-1/1
Timer0 Rate
TMR0IE
TRISA5
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
Bit 5
—
TMR0SE
R/W-1/1
TRISA4
Preliminary
INTE
Bit 4
—
OSC
/4)
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
CPSRNG1 CPSRNG0 CPSOUT
R/W-1/1
TRISA3
IOCIE
Bit 3
PSA
PSA
TMR0IF
TRISA2
Bit 2
PS2
R/W-1/1
PIC12(L)F1840
TRISA1
Bit 1
INTF
PS1
PS<2:0>
R/W-1/1
TRISA0
T0XCS
IOCIF
Bit 0
PS0
DS41441B-page 161
R/W-1/1
Register
on Page
159*
301
161
115
83
bit 0