PIC12F1840-I/P Microchip Technology, PIC12F1840-I/P Datasheet - Page 197

• Manufacturer Part Number: PIC12F1840-I/P
• Description: 7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core 8 PDI
• Manufacturer: Microchip Technology

Specifications of PIC12F1840-I/P

• Processor Series: PIC12F
• Core: PIC
• Program Memory Type: Flash
• Program Memory Size: 7 KB
• Data Ram Size: 256 B
• Interface Type: MI2C, SPI, EUSART
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Package / Case: PDIP-8
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

24.3.6
In Sleep mode, the TMR2 register will not increment
and the state of the module will not change. If the CCP1
pin is driving a value, it will continue to drive that value.
When the device wakes up, TMR2 will continue from its
previous state.
24.3.7
The PWM frequency is derived from the system clock
frequency. Any changes in the system clock frequency
will result in changes to the PWM frequency. See
Section 5.0 “Oscillator Module (With Fail-Safe
Clock Monitor)”
24.3.8
Any Reset will force all ports to Input mode and the
CCP registers to their Reset states.
TABLE 24-7:
 2011 Microchip Technology Inc.
APFCON
CCP1CON
INTCON
PIE1
PIR1
PR2
T2CON
TMR2
TRISA
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the PWM.
Name
*
Page provides register information.
OPERATION IN SLEEP MODE
CHANGES IN SYSTEM CLOCK
FREQUENCY
EFFECTS OF RESET
Timer2 Period Register
Timer2 Module Register
RXDTSEL
TMR1GIE
TMR1GIF
Bit 7
GIE
for additional details.
—
—
SUMMARY OF REGISTERS ASSOCIATED WITH STANDARD PWM
P1M<1:0>
SDOSEL
PEIE
ADIE
ADIF
Bit 6
—
TMR0IE
TRISA5
SSSEL
RCIE
RCIF
Bit 5
T2OUTPS<3:0>
DC1B<1:0>
TRISA4
Preliminary
INTE
TXIE
Bit 4
TXIF
—
T1GSEL
SSP1IE
SSP1IF
TRISA3
IOCIE
24.3.9
This module incorporates I/O pins that can be moved to
other locations with the use of the alternate pin function
register, APFCON. To determine which pins can be
moved and what their default locations are upon a
reset, see
more information.
Bit 3
TXCKSEL
TMR2ON
TMR0IF
CCP1IE
CCP1IF
TRISA2
Section 12.1 “Alternate Pin Function”
ALTERNATE PIN LOCATIONS
Bit 2
CCP1M<3:0>
PIC12(L)F1840
P1BSEL
TMR2IE
TMR2IF
TRISA1
INTF
Bit 1
T2CKPS<1:0>
CCP1SEL
TMR1IE
TMR1IF
TRISA0
IOCIF
Bit 0
DS41441B-page 197
Register
on Page
175*
207
177
175
112
115
83
84
86
for