PIC12F1840-I/P Microchip Technology, PIC12F1840-I/P Datasheet - Page 235

• Manufacturer Part Number: PIC12F1840-I/P
• Description: 7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core 8 PDI
• Manufacturer: Microchip Technology

Specifications of PIC12F1840-I/P

• Processor Series: PIC12F
• Core: PIC
• Program Memory Type: Flash
• Program Memory Size: 7 KB
• Data Ram Size: 256 B
• Interface Type: MI2C, SPI, EUSART
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Package / Case: PDIP-8
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

25.5.3.3
Setting the AHEN bit of the SSP1CON3 register
enables additional clock stretching and interrupt gen-
eration after the 8th falling edge of a received match-
ing address. Once a matching address has been
clocked in, CKP is cleared and the SSP1IF interrupt is
set.
Figure 25-18
Address Slave Transmission with AHEN enabled.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Slave hardware automatically clears the CKP bit
11. Slave software clears SSP1IF.
12. Slave loads value to transmit to the master into
13. Slave sets CKP bit releasing the clock.
14. Master clocks out the data from the slave and
15. Slave hardware copies the ACK value into the
16. Steps 10-15 are repeated for each byte transmit-
17. If the master sends a not ACK the slave
 2011 Microchip Technology Inc.
Note: SSP1BUF cannot be loaded until after the
Note: Master must send a not ACK on the last byte
Bus starts Idle.
Master sends Start condition; the S bit of
SSP1STAT is set; SSP1IF is set if inter-
rupt-on-Start detect is enabled.
Master sends matching address with R/W bit
set. After the 8th falling edge of the SCL line the
CKP bit is cleared and SSP1IF interrupt is gen-
erated.
Slave software clears SSP1IF.
Slave software reads ACKTIM bit of SSP1CON3
register, and R/W and D/A of the SSP1STAT
register to determine the source of the interrupt.
Slave reads the address value from the
SSP1BUF register clearing the BF bit.
Slave software decides from this information if it
wishes to ACK or not ACK and sets ACKDT bit
of the SSP1CON2 register accordingly.
Slave sets the CKP bit releasing SCL.
Master clocks in the ACK value from the slave.
and sets SSP1IF after the ACK if the R/W bit is
set.
SSP1BUF setting the BF bit.
sends an ACK value on the 9th SCL pulse.
ACKSTAT bit of the SSP1CON2 register.
ted to the master from the slave.
releases the bus, allowing the master to send a
Stop and end the communication.
ACK.
to ensure that the slave releases the SCL
line to receive a Stop.
7-bit Transmission with Address
Hold Enabled
displays a standard waveform of a 7-bit
Preliminary
PIC12(L)F1840
DS41441B-page 235