PIC12F1840-I/P Microchip Technology, PIC12F1840-I/P Datasheet - Page 263

• Manufacturer Part Number: PIC12F1840-I/P
• Description: 7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core 8 PDI
• Manufacturer: Microchip Technology

Specifications of PIC12F1840-I/P

• Processor Series: PIC12F
• Core: PIC
• Program Memory Type: Flash
• Program Memory Size: 7 KB
• Data Ram Size: 256 B
• Interface Type: MI2C, SPI, EUSART
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Package / Case: PDIP-8
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

REGISTER 25-4:
 2011 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
ACKTIM
R-0/0
2:
3:
For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSP1OV is still set
when a new byte is received and BF = 1, but hardware continues to write the most recent byte to
SSP1BUF.
This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled.
The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set.
ACKTIM: Acknowledge Time Status bit (I
1 = Indicates the I
0 = Not an Acknowledge sequence, cleared on 9
PCIE: Stop Condition Interrupt Enable bit (I
1 = Enable interrupt on detection of Stop condition
0 = Stop detection interrupts are disabled
SCIE: Start Condition Interrupt Enable bit (I
1 = Enable interrupt on detection of Start or Restart conditions
0 = Start detection interrupts are disabled
BOEN: Buffer Overwrite Enable bit
In SPI Slave mode:
In I
In I
SDAHT: SDA Hold Time Selection bit (I
1 = Minimum of 300 ns hold time on SDA after the falling edge of SCL
0 = Minimum of 100 ns hold time on SDA after the falling edge of SCL
SBCDE: Slave Mode Bus Collision Detect Enable bit (I
If on the rising edge of SCL, SDA is sampled low when the module is outputting a high state, the
BCL1IF bit of the PIR2 register is set, and bus goes Idle
1 = Enable slave bus collision interrupts
0 = Slave bus collision interrupts are disabled
AHEN: Address Hold Enable bit (I
1 = Following the 8th falling edge of SCL for a matching received address byte; CKP bit of the
0 = Address holding is disabled
DHEN: Data Hold Enable bit (I
1 = Following the 8th falling edge of SCL for a received data byte; slave hardware clears the CKP bit
0 = Data holding is disabled
R/W-0/0
2
2
PCIE
C Master mode and SPI Master mode:
C Slave mode:
This bit is ignored.
1 = SSP1BUF updates every time that a new data byte is shifted in ignoring the BF bit
0 = If new byte is received with BF bit of the SSP1STAT register already set, SSP1OV bit of the
1 = SSP1BUF is updated and ACK is generated for a received address/data byte, ignoring the
0 = SSP1BUF is only updated when SSP1OV is clear
SSP1CON1 register will be cleared and the SCL will be held low.
of the SSP1CON1 register and SCL is held low.
SSP1CON3: SSP1 CONTROL REGISTER 3
SSP1CON1 register is set, and the buffer is not updated
state of the SSP1OV bit only if the BF bit = 0.
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
R/W-0/0
2
SCIE
C bus is in an Acknowledge sequence, set on 8
(1)
2
R/W-0/0
C Slave mode only)
BOEN
2
Preliminary
C Slave mode only)
2
C mode only)
2
(2)
(2)
C mode only)
2
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
2
C mode only)
C mode only)
R/W-0/0
SDAHT
TH
rising edge of SCL clock
2
(3)
C Slave mode only)
R/W-0/0
SBCDE
PIC12(L)F1840
TH
falling edge of SCL clock
R/W-0/0
AHEN
DS41441B-page 263
R/W-0/0
DHEN
bit 0