PIC12F1840-I/P Microchip Technology, PIC12F1840-I/P Datasheet - Page 375

• Manufacturer Part Number: PIC12F1840-I/P
• Description: 7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core 8 PDI
• Manufacturer: Microchip Technology

Specifications of PIC12F1840-I/P

• Processor Series: PIC12F
• Core: PIC
• Program Memory Type: Flash
• Program Memory Size: 7 KB
• Data Ram Size: 256 B
• Interface Type: MI2C, SPI, EUSART
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Package / Case: PDIP-8
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Extended Instruction Set
F
Fail-Safe Clock Monitor....................................................... 59
Firmware Instructions........................................................ 307
Fixed Voltage Reference (FVR) ........................................ 123
Flash Program Memory ...................................................... 97
FSR Register ................ 24, 25, 26, 27, 28, 29, 30, 31, 32, 33
FVRCON (Fixed Voltage Reference Control) Register ..... 124
I
I
INDF Register ............... 24, 25, 26, 27, 28, 29, 30, 31, 32, 33
Indirect Addressing ............................................................. 37
Instruction Format ............................................................. 308
Instruction Set ................................................................... 307
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2
C Mode (MSSPx)
ADDFSR ................................................................... 311
Fail-Safe Condition Clearing ....................................... 59
Fail-Safe Detection ..................................................... 59
Fail-Safe Operation..................................................... 59
Reset or Wake-up from Sleep..................................... 59
Associated Registers ................................................ 124
Erasing...................................................................... 102
Modifying................................................................... 106
Writing....................................................................... 102
Acknowledge Sequence Timing................................ 251
Bus Collision
Effects of a Reset...................................................... 252
I
Master Mode
Multi-Master Communication, Bus Collision and
Multi-Master Mode .................................................... 252
Read/Write Bit Information (R/W Bit) ........................ 228
Slave Mode
Sleep Operation ........................................................ 252
Stop Condition Timing............................................... 251
ADDLW ..................................................................... 311
ADDWF..................................................................... 311
ADDWFC .................................................................. 311
ANDLW ..................................................................... 311
ANDWF..................................................................... 311
BRA........................................................................... 312
CALL ......................................................................... 313
CALLW...................................................................... 313
LSLF ......................................................................... 315
LSRF......................................................................... 315
MOVF........................................................................ 315
MOVIW ..................................................................... 316
MOVLB ..................................................................... 316
MOVWI ..................................................................... 317
OPTION .................................................................... 317
RESET ...................................................................... 317
SUBWFB................................................................... 319
2
C Clock Rate w/BRG.............................................. 259
Associated Registers
Reception.......................................................... 293
Transmission .................................................... 292
During a Repeated Start Condition ................... 256
During a Stop Condition.................................... 257
Operation .......................................................... 243
Reception.......................................................... 249
Start Condition Timing .............................. 245, 246
Transmission .................................................... 247
Arbitration ......................................................... 252
Transmission .................................................... 233
Receive..................................................... 293
Transmit.................................................... 292
Preliminary
INTCON Register................................................................ 83
Internal Oscillator Block
Internal Sampling Switch (R
Internet Address ............................................................... 379
Interrupt-On-Change......................................................... 119
Interrupts ............................................................................ 77
INTOSC Specifications ..................................................... 337
IOCAF Register ................................................................ 120
IOCAN Register ................................................................ 120
IOCAP Register ................................................................ 120
L
LATA Register .................................................................. 116
Load Conditions................................................................ 335
LSLF ................................................................................. 315
LSRF ................................................................................ 315
M
Master Synchronous Serial Port. See MSSPx
MCLR ................................................................................. 72
MDCARH Register............................................................ 186
MDCARL Register ............................................................ 187
MDCON Register.............................................................. 184
MDSRC Register .............................................................. 185
Memory Organization ......................................................... 15
TRIS ......................................................................... 320
BCF .......................................................................... 312
BSF........................................................................... 312
BTFSC...................................................................... 312
BTFSS ...................................................................... 312
CALL......................................................................... 313
CLRF ........................................................................ 313
CLRW ....................................................................... 313
CLRWDT .................................................................. 313
COMF ....................................................................... 313
DECF........................................................................ 313
DECFSZ ................................................................... 314
GOTO ....................................................................... 314
INCF ......................................................................... 314
INCFSZ..................................................................... 314
IORLW ...................................................................... 314
IORWF...................................................................... 314
MOVLW .................................................................... 316
MOVWF.................................................................... 316
NOP.......................................................................... 317
RETFIE..................................................................... 318
RETLW ..................................................................... 318
RETURN................................................................... 318
RLF........................................................................... 318
RRF .......................................................................... 319
SLEEP ...................................................................... 319
SUBLW..................................................................... 319
SUBWF..................................................................... 319
SWAPF..................................................................... 320
XORLW .................................................................... 320
XORWF .................................................................... 320
INTOSC
Associated Registers................................................ 121
ADC .......................................................................... 132
Associated registers w/ Interrupts .............................. 88
Configuration Word w/ Clock Sources........................ 63
Configuration Word w/ Reference Clock Sources ...... 67
TMR1........................................................................ 167
Internal........................................................................ 72
Data ............................................................................ 17
Specifications ................................................... 337
PIC12(L)F1840
SS
) Impedance ..................... 137
DS041441B-page 375