PIC12F1840-I/P Microchip Technology, PIC12F1840-I/P Datasheet - Page 251

• Manufacturer Part Number: PIC12F1840-I/P
• Description: 7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core 8 PDI
• Manufacturer: Microchip Technology

Specifications of PIC12F1840-I/P

• Processor Series: PIC12F
• Core: PIC
• Program Memory Type: Flash
• Program Memory Size: 7 KB
• Data Ram Size: 256 B
• Interface Type: MI2C, SPI, EUSART
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Package / Case: PDIP-8
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

25.6.8
An Acknowledge sequence is enabled by setting the
Acknowledge Sequence Enable bit, ACKEN bit of the
SSP1CON2 register. When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDA pin. If the user wishes to gen-
erate an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The Baud Rate
Generator then counts for one rollover period (T
and the SCL pin is deasserted (pulled high). When the
SCL pin is sampled high (clock arbitration), the Baud
Rate Generator counts for T
pulled low. Following this, the ACKEN bit is automatically
cleared, the Baud Rate Generator is turned off and the
MSSP1
(Figure
25.6.8.1
If the user writes the SSP1BUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write does
not occur).
FIGURE 25-30:
 2011 Microchip Technology Inc.
25-29).
module
Note: T
ACKNOWLEDGE SEQUENCE
TIMING
WCOL Status Flag
SSP1IF
BRG
Acknowledge sequence starts here,
SDA
SCL
then
= one Baud Rate Generator period.
ACKNOWLEDGE SEQUENCE WAVEFORM
SSP1IF set at
the end of receive
goes
BRG
ACKEN = 1, ACKDT = 0
. The SCL pin is then
write to SSP1CON2
into
Idle
8
D0
mode
BRG
Preliminary
)
Cleared in
software
T
BRG
ACK
25.6.9
A Stop bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN bit of the SSP1CON2 register. At the end of a
receive/transmit, the SCL line is held low after the
falling edge of the ninth clock. When the PEN bit is set,
the master will assert the SDA line low. When the SDA
line is sampled low, the Baud Rate Generator is
reloaded and counts down to ‘0’. When the Baud Rate
Generator times out, the SCL pin will be brought high
and one T
later, the SDA pin will be deasserted. When the SDA
pin is sampled high while SCL is high, the P bit of the
SSP1STAT register is set. A T
cleared and the SSP1IF bit is set
25.6.9.1
If the user writes the SSP1BUF when a Stop sequence
is in progress, then the WCOL bit is set and the
contents of the buffer are unchanged (the write does
not occur).
T
BRG
9
SSP1IF set at the end
of Acknowledge sequence
BRG
STOP CONDITION TIMING
WCOL Status Flag
ACKEN automatically cleared
(Baud Rate Generator rollover count)
PIC12(L)F1840
Cleared in
software
BRG
(Figure
later, the PEN bit is
DS41441B-page 251
25-30).