PIC12F1840-I/P Microchip Technology, PIC12F1840-I/P Datasheet - Page 102

• Manufacturer Part Number: PIC12F1840-I/P
• Description: 7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core 8 PDI
• Manufacturer: Microchip Technology

Specifications of PIC12F1840-I/P

• Processor Series: PIC12F
• Core: PIC
• Program Memory Type: Flash
• Program Memory Size: 7 KB
• Data Ram Size: 256 B
• Interface Type: MI2C, SPI, EUSART
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Package / Case: PDIP-8
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC12(L)F1840
11.3.2
While executing code, program memory can only be
erased by rows. To erase a row:
1.
2.
3.
4.
5.
6.
See
After the “BSF EECON1,WR” instruction, the processor
requires two cycles to set up the erase operation. The
user must place two NOP instructions after the WR bit is
set. The processor will halt internal operations for the
typical 2 ms erase time. This is not Sleep mode as the
clocks and peripherals will continue to run. After the
erase cycle, the processor will resume operation with
the third instruction after the EECON1 write instruction.
11.3.3
Program memory is programmed using the following
steps:
1.
2.
3.
4.
Before writing to program memory, the word(s) to be
written must be erased or previously unwritten. Pro-
gram memory can only be erased one row at a time. No
automatic erase occurs upon the initiation of the write.
Program memory can be written one or more words at
a time. The maximum number of words written at one
time is equal to the number of write latches. See
Figure 11-2
write latches) for more details. The write latches are
aligned to the address boundary defined by EEADRL
as shown in
these boundaries. At the completion of a program
memory write operation, the write latches are reset to
contain 0x3FFF.
DS41441B-page 102
Load the EEADRH:EEADRL register pair with
the address of new row to be erased.
Clear the CFGS bit of the EECON1 register.
Set the EEPGD, FREE and WREN bits of the
EECON1 register.
Write 55h, then AAh, to EECON2 (Flash
programming unlock sequence).
Set control bit WR of the EECON1 register to
begin the erase operation.
Poll the FREE bit in the EECON1 register to
determine when the row erase has completed.
Load the starting address of the word(s) to be
programmed.
Load the write latches with data.
Initiate a programming operation.
Repeat steps 1 through 3 until all data is written.
Example
ERASING FLASH PROGRAM
MEMORY
WRITING TO FLASH PROGRAM
MEMORY
(block writes to program memory with 32
Table
11-4.
11-1. Write operations do not cross
Preliminary
The following steps should be completed to load the
write latches and program a block of program memory.
These steps are divided into two parts. First, all write
latches are loaded with data except for the last program
memory location. Then, the last write latch is loaded
and the programming sequence is initiated. A special
unlock sequence is required to load a write latch with
data or initiate a Flash programming operation. This
unlock sequence should not be interrupted.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Load the EEDATH:EEDATL register pair with
11. Write 55h, then AAh, to EECON2, then set the
It is not necessary to load the entire write latch block
with user program data. However, the entire write latch
block will be written to program memory.
An example of the complete write sequence for 32
words is shown in
loaded into the EEADRH:EEADRL register pair; the 32
words of data are loaded using indirect addressing.
Set the EEPGD and WREN bits of the EECON1
register.
Clear the CFGS bit of the EECON1 register.
Set the LWLO bit of the EECON1 register. When
the LWLO bit of the EECON1 register is ‘1’, the
write sequence will only load the write latches
and will not initiate the write to Flash program
memory.
Load the EEADRH:EEADRL register pair with
the address of the location to be written.
Load the EEDATH:EEDATL register pair with
the program memory data to be written.
Write 55h, then AAh, to EECON2, then set the
WR bit of the EECON1 register (Flash
programming unlock sequence). The write latch
is now loaded.
Increment the EEADRH:EEADRL register pair
to point to the next location.
Repeat steps 5 through 7 until all but the last
write latch has been loaded.
Clear the LWLO bit of the EECON1 register.
When the LWLO bit of the EECON1 register is
‘0’, the write sequence will initiate the write to
Flash program memory.
the program memory data to be written.
WR bit of the EECON1 register (Flash
programming unlock sequence). The entire
latch block is now written to Flash program
memory.
Example
 2011 Microchip Technology Inc.
11-5. The initial address is