PIC12F1840-I/P Microchip Technology, PIC12F1840-I/P Datasheet - Page 378

• Manufacturer Part Number: PIC12F1840-I/P
• Description: 7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core 8 PDI
• Manufacturer: Microchip Technology

Specifications of PIC12F1840-I/P

• Processor Series: PIC12F
• Core: PIC
• Program Memory Type: Flash
• Program Memory Size: 7 KB
• Data Ram Size: 256 B
• Interface Type: MI2C, SPI, EUSART
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Package / Case: PDIP-8
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC12(L)F1840
Timing Diagrams and Specifications
Timing Parameter Symbology........................................... 335
Timing Requirements
TMR0 Register .................................................................... 24
TMR1H Register ................................................................. 24
TMR1L Register .................................................................. 24
TMR2 Register .................................................................... 24
TRIS .................................................................................. 320
TRISA Register ........................................................... 25, 115
Two-Speed Clock Start-up Mode ........................................ 57
TXREG.............................................................................. 269
TXREG Register ................................................................. 27
DS041441B-page 378
Baud Rate Generator with Clock Arbitration ............. 244
BRG Reset Due to SDA Arbitration During Start
Brown-out Reset (BOR) ............................................ 340
Brown-out Reset Situations ........................................ 71
Bus Collision During a Repeated Start Condition
Bus Collision During a Repeated Start Condition
Bus Collision During a Start Condition (SCL = 0) ..... 255
Bus Collision During a Stop Condition (Case 1) ....... 257
Bus Collision During a Stop Condition (Case 2) ....... 257
Bus Collision During Start Condition (SDA only) ...... 254
Bus Collision for Transmit and Acknowledge............ 253
CLKOUT and I/O....................................................... 338
Clock Synchronization .............................................. 241
Clock Timing ............................................................. 336
Comparator Output ................................................... 151
Enhanced Capture/Compare/PWM (ECCP) ............. 343
Fail-Safe Clock Monitor (FSCM) ................................. 60
First Start Bit Timing ................................................. 245
Half-Bridge PWM Output .................................. 200, 203
I
I
I
I
I
INT Pin Interrupt.......................................................... 81
Internal Oscillator Switch Timing................................. 55
PWM Auto-shutdown ................................................ 202
PWM Output (Active-High)........................................ 199
PWM Output (Active-Low) ........................................ 199
Repeat Start Condition.............................................. 246
Reset Start-up Sequence............................................ 73
Reset, WDT, OST and Power-up Timer ................... 339
Send Break Character Sequence ............................. 287
SPI Master Mode (CKE = 1, SMP = 1) ..................... 348
SPI Mode (Master Mode) .......................................... 218
SPI Slave Mode (CKE = 0) ....................................... 349
SPI Slave Mode (CKE = 1) ....................................... 349
Synchronous Reception (Master Mode, SREN) ....... 291
Synchronous Transmission....................................... 289
Synchronous Transmission (Through TXEN) ........... 289
Timer0 and Timer1 External Clock ........................... 342
Timer1 Incrementing Edge........................................ 167
Two Speed Start-up .................................................... 58
USART Synchronous Receive (Master/Slave) ......... 347
USART Synchronous Transmission (Master/Slave) . 346
Wake-up from Interrupt ............................................... 90
PLL Clock.................................................................. 337
I
SPI Mode .................................................................. 350
2
2
2
2
2
2
C Bus Data ............................................................. 351
C Bus Start/Stop Bits.............................................. 350
C Master Mode (7 or 10-Bit Transmission) ............ 248
C Master Mode (7-Bit Reception) ........................... 250
C Stop Condition Receive or Transmit Mode ......... 252
C Bus Data ............................................................. 352
Condition........................................................... 255
(Case 1) ............................................................ 256
(Case 2) ............................................................ 256
Firmware Restart .............................................. 201
Preliminary
TXSTA Register.......................................................... 27, 276
U
USART
V
V
VREGCON Register ........................................................... 91
W
Wake-up on Break ............................................................ 285
Wake-up Using Interrupts ................................................... 90
Watchdog Timer (WDT)...................................................... 72
WCOL ....................................................... 244, 247, 249, 251
WCOL Status Flag.................................... 244, 247, 249, 251
WDTCON Register ............................................................. 95
WPUB Register................................................................. 117
Write Protection .................................................................. 45
WWW Address ................................................................. 379
WWW, On-Line Support ....................................................... 7
REF
BRGH Bit .................................................................. 279
Synchronous Master Mode
Modes ......................................................................... 94
Specifications ........................................................... 341
. S
EE
Requirements, Synchronous Receive .............. 347
Requirements, Synchronous Transmission...... 347
Timing Diagram, Synchronous Receive ........... 347
Timing Diagram, Synchronous Transmission... 346
ADC Reference Voltage
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