PIC12F1840-I/P Microchip Technology, PIC12F1840-I/P Datasheet - Page 215

• Manufacturer Part Number: PIC12F1840-I/P
• Description: 7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core 8 PDI
• Manufacturer: Microchip Technology

Specifications of PIC12F1840-I/P

• Processor Series: PIC12F
• Core: PIC
• Program Memory Type: Flash
• Program Memory Size: 7 KB
• Data Ram Size: 256 B
• Interface Type: MI2C, SPI, EUSART
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Package / Case: PDIP-8
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

FIGURE 25-4:
25.2.1
The MSSP1 module has five registers for SPI mode
operation. These are:
• MSSP1 STATUS register (SSP1STAT)
• MSSP1 Control Register 1 (SSP1CON1)
• MSSP1 Control Register 3 (SSP1CON3)
• MSSP1 Data Buffer register (SSP1BUF)
• MSSP1 Address register (SSP1ADD)
• MSSP1 Shift register (SSP1SR)
SSP1CON1 and SSP1STAT are the control and
STATUS registers in SPI mode operation. The
SSP1CON1 register is readable and writable. The
lower 6 bits of the SSP1STAT are read-only. The upper
two bits of the SSP1STAT are read/write.
In one SPI master mode, SSP1ADD can be loaded
with a value used in the Baud Rate Generator. More
information on the Baud Rate Generator is available in
Section 25.7 “Baud Rate
SSP1SR is the shift register used for shifting data in
and out. SSP1BUF provides indirect access to the
SSP1SR register. SSP1BUF is the buffer register to
which data bytes are written, and from which data
bytes are read.
In receive operations, SSP1SR and SSP1BUF
together create a buffered receiver. When SSP1SR
receives a complete byte, it is transferred to SSP1BUF
and the SSP1IF interrupt is set.
During transmission, the SSP1BUF is not buffered. A
write to SSP1BUF will write to both SSP1BUF and
SSP1SR.
 2011 Microchip Technology Inc.
(Not directly accessible)
SPI MODE REGISTERS
SPI Master
SPI MASTER AND MULTIPLE SLAVE CONNECTION
Generator”.
General I/O
General I/O
General I/O
SDO
SCK
SDI
Preliminary
SCK
SDI
SDO
SS
SCK
SDI
SDO
SS
SCK
SDI
SDO
SS
PIC12(L)F1840
SPI Slave
SPI Slave
SPI Slave
#1
#2
#3
DS41441B-page 215