PIC12F1840-I/P Microchip Technology, PIC12F1840-I/P Datasheet - Page 218

• Manufacturer Part Number: PIC12F1840-I/P
• Description: 7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core 8 PDI
• Manufacturer: Microchip Technology

Specifications of PIC12F1840-I/P

• Processor Series: PIC12F
• Core: PIC
• Program Memory Type: Flash
• Program Memory Size: 7 KB
• Data Ram Size: 256 B
• Interface Type: MI2C, SPI, EUSART
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Package / Case: PDIP-8
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC12(L)F1840
25.2.3
The master can initiate the data transfer at any time
because it controls the SCK line. The master
determines when the slave (Processor 2,
is to broadcast data by the software protocol.
In Master mode, the data is transmitted/received as
soon as the SSP1BUF register is written to. If the SPI
is only going to receive, the SDO output could be dis-
abled (programmed as an input). The SSP1SR register
will continue to shift in the signal present on the SDI pin
at the programmed clock rate. As each byte is
received, it will be loaded into the SSP1BUF register as
if a normal received byte (interrupts and Status bits
appropriately set).
FIGURE 25-6:
DS41441B-page 218
Write to
SSP1BUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
SDO
(CKE = 0)
SDO
(CKE = 1)
SDI
(SMP = 0)
Input
Sample
(SMP = 0)
SDI
(SMP = 1)
Input
Sample
(SMP = 1)
SSP1IF
SSP1SR to
SSP1BUF
SPI MASTER MODE
SPI MODE WAVEFORM (MASTER MODE)
bit 7
bit 7
bit 7
bit 7
bit 6
bit 6
Figure
bit 5
bit 5
25-5)
Preliminary
bit 4
bit 4
bit 3
bit 3
The clock polarity is selected by appropriately
programming the CKP bit of the SSP1CON1 register
and the CKE bit of the SSP1STAT register. This then,
would give waveforms for SPI communication as
shown in
where the MSB is transmitted first. In Master mode, the
SPI clock rate (bit rate) is user programmable to be one
of the following:
• F
• F
• F
• Timer2 output/2
• Fosc/(4 * (SSP1ADD + 1))
Figure 25-6
When the CKE bit is set, the SDO data is valid before
there is a clock edge on SCK. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSP1BUF is loaded with the received
data is shown.
OSC
OSC
OSC
/4 (or T
/16 (or 4 * T
/64 (or 16 * T
bit 2
bit 2
Figure
shows the waveforms for Master mode.
CY
)
bit 1
bit 1
25-6,
CY
CY
)
)
 2011 Microchip Technology Inc.
Figure 25-8
bit 0
bit 0
bit 0
bit 0
and
4 Clock
Modes
Figure
25-9,