PIC12F1840-I/P Microchip Technology, PIC12F1840-I/P Datasheet - Page 190

• Manufacturer Part Number: PIC12F1840-I/P
• Description: 7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core 8 PDI
• Manufacturer: Microchip Technology

Specifications of PIC12F1840-I/P

• Processor Series: PIC12F
• Core: PIC
• Program Memory Type: Flash
• Program Memory Size: 7 KB
• Data Ram Size: 256 B
• Interface Type: MI2C, SPI, EUSART
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Package / Case: PDIP-8
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC12(L)F1840
24.1
Capture mode makes use of the 16-bit Timer1
resource. When an event occurs on the CCP1 pin, the
16-bit CCPR1H:CCPR1L register pair captures and
stores the 16-bit value of the TMR1H:TMR1L register
pair, respectively. An event is defined as one of the
following and is configured by the CCP1M<3:0> bits of
the CCP1CON register:
• Every falling edge
• Every rising edge
• Every 4th rising edge
• Every 16th rising edge
When a capture is made, the Interrupt Request Flag bit
CCP1IF of the PIR1 register is set. The interrupt flag
must be cleared in software. If another capture occurs
before the value in the CCPR1H, CCPR1L register pair
is read, the old captured value is overwritten by the new
captured value.
Figure 24-1
operation.
24.1.1
In Capture mode, the CCP1 pin should be configured
as an input by setting the associated TRIS control bit.
Also, the CCP1 pin function may be moved to
alternative pins using the APFCON register. Refer to
Section 12.1 “Alternate Pin Function”
details.
FIGURE 24-1:
DS41441B-page 190
CCP1
pin
Note:
System Clock (F
Capture Mode
Edge Detect
CCP1 PIN CONFIGURATION
If the CCP1 pin is configured as an output,
a write to the port can cause a capture
condition.
Prescaler
 1, 4, 16
shows a simplified diagram of the capture
and
CCP1M<3:0>
OSC
)
Set Flag bit CCP1IF
(PIR1 register)
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
Capture
Enable
CCPR1H
TMR1H
CCPR1L
for more
TMR1L
Preliminary
24.1.2
Timer1 must be running in Timer mode or Synchronized
Counter mode for the CCP1 module to use the capture
feature. In Asynchronous Counter mode, the capture
operation may not work.
See
for more information on configuring Timer1.
24.1.3
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep the
CCP1IE interrupt enable bit of the PIE1 register clear to
avoid false interrupts. Additionally, the user should
clear the CCP1IF interrupt flag bit of the PIR1 register
following any change in Operating mode.
24.1.4
There are four prescaler settings specified by the
CCP1M<3:0>
Whenever the CCP1 module is turned off, or the CCP1
module is not in Capture mode, the prescaler counter
is cleared. Any Reset will clear the prescaler counter.
Switching from one capture prescaler to another does not
clear the prescaler and may generate a false interrupt. To
avoid this unexpected operation, turn the module off by
clearing the CCP1CON register before changing the
prescaler.
perform this function.
EXAMPLE 24-1:
BANKSEL CCP1CON
CLRF
MOVLW
MOVWF
Note:
Section 21.0 “Timer1 Module with Gate Control”
CCP1CON
NEW_CAPT_PS ;Load the W reg with
CCP1CON
Example 24-1
TIMER1 MODE RESOURCE
SOFTWARE INTERRUPT MODE
Clocking Timer1 from the system clock
(F
mode. In order for Capture mode to
recognize the trigger event on the CCP1
pin, Timer1 must be clocked from the
instruction clock (F
external clock source.
CCP1 PRESCALER
OSC
bits
) should not be used in Capture
of
CHANGING BETWEEN
CAPTURE PRESCALERS
;Set Bank bits to point
;to CCP1CON
;Turn CCP1 module off
;the new prescaler
;move value and CCP1 ON
;Load CCP1CON with this
;value
 2011 Microchip Technology Inc.
demonstrates the code to
the
OSC
CCP1CON
/4) or from an
register.