PIC12F1840-I/P Microchip Technology, PIC12F1840-I/P Datasheet - Page 212

• Manufacturer Part Number: PIC12F1840-I/P
• Description: 7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core 8 PDI
• Manufacturer: Microchip Technology

Specifications of PIC12F1840-I/P

• Processor Series: PIC12F
• Core: PIC
• Program Memory Type: Flash
• Program Memory Size: 7 KB
• Data Ram Size: 256 B
• Interface Type: MI2C, SPI, EUSART
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Package / Case: PDIP-8
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC12(L)F1840
The I
features:
• Master mode
• Slave mode
• Byte NACKing (Slave mode)
• Limited Multi-master support
• 7-bit and 10-bit addressing
• Start and Stop interrupts
• Interrupt masking
• Clock stretching
• Bus collision detection
• General call address matching
• Address masking
• Address Hold and Data Hold modes
• Selectable SDA hold times
Figure 25-2
ule in Master mode.
interface module in Slave mode.
FIGURE 25-2:
DS41441B-page 212
2
C interface supports the following modes and
SDA
SCL
is a block diagram of the I
Figure 25-3
MSSP1 BLOCK DIAGRAM (I
SDA in
is a diagram of the I
Bus Collision
SCL in
2
C interface mod-
Read
MSb
Generate (SSP1CON2)
Address Match detect
Preliminary
Write collision detect
2
end of XMIT/RCV
Start bit, Stop bit,
State counter for
Clock arbitration
C
Start bit detect,
Stop bit detect
Acknowledge
SSP1BUF
SSP1SR
2
C™ MASTER MODE)
LSb
Write
Clock
Shift
data bus
Internal
Set/Reset: S, P, SSP1STAT, WCOL, SSP1OV
Reset SEN, PEN (SSP1CON2)
Set SSP1IF, BCL1IF
 2011 Microchip Technology Inc.
[SSP1M 3:0]
Baud rate
generator
(SSP1ADD)