PIC12F1840-I/P Microchip Technology, PIC12F1840-I/P Datasheet - Page 130

7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core 8 PDI

PIC12F1840-I/P

Manufacturer Part Number
PIC12F1840-I/P
Description
7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core 8 PDI
Manufacturer
Microchip Technology
Datasheet

Specifications of PIC12F1840-I/P

Processor Series
PIC12F
Core
PIC
Program Memory Type
Flash
Program Memory Size
7 KB
Data Ram Size
256 B
Interface Type
MI2C, SPI, EUSART
Number Of Timers
3
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Package / Case
PDIP-8
Development Tools By Supplier
MPLAB IDE Software
Minimum Operating Temperature
- 40 C
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC12F1840-I/P
Manufacturer:
MICROCHIP
Quantity:
200
PIC12(L)F1840
16.1.5
The ADC module allows for the ability to generate an
interrupt upon completion of an Analog-to-Digital
conversion. The ADC Interrupt Flag is the ADIF bit in
the PIR1 register. The ADC Interrupt Enable is the
ADIE bit in the PIE1 register. The ADIF bit must be
cleared in software.
This interrupt can be generated while the device is
operating or while in Sleep. If the device is in Sleep, the
interrupt will wake-up the device. Upon waking from
Sleep, the next instruction following the SLEEP instruc-
tion is always executed. If the user is attempting to
wake-up from Sleep and resume in-line code execu-
tion, the GIE and PEIE bits of the INTCON register
must be disabled. If the GIE and PEIE bits of the
INTCON register are enabled, execution will switch to
the Interrupt Service Routine.
FIGURE 16-3:
DS41441B-page 130
Note 1: The ADIF bit is set at the completion of
(ADFM = 0)
(ADFM = 1)
2: The ADC operates during Sleep only
INTERRUPTS
every conversion, regardless of whether
or not the ADC interrupt is enabled.
when the F
10-BIT A/D CONVERSION RESULT FORMAT
MSB
bit 7
bit 7
RC
Unimplemented: Read as ‘0’
oscillator is selected.
ADRESH
10-bit A/D Result
Preliminary
MSB
bit 0
bit 0
16.1.6
The 10-bit A/D conversion result can be supplied in two
formats, left justified or right justified. The ADFM bit of
the ADCON1 register controls the output format.
Figure 16-3
bit 7
bit 7
RESULT FORMATTING
shows the two output formats.
10-bit A/D Result
LSB
Unimplemented: Read as ‘0’
 2011 Microchip Technology Inc.
ADRESL
bit 0
LSB
bit 0

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