PIC12F1840-I/P Microchip Technology, PIC12F1840-I/P Datasheet - Page 21

• Manufacturer Part Number: PIC12F1840-I/P
• Description: 7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core 8 PDI
• Manufacturer: Microchip Technology

Specifications of PIC12F1840-I/P

• Processor Series: PIC12F
• Core: PIC
• Program Memory Type: Flash
• Program Memory Size: 7 KB
• Data Ram Size: 256 B
• Interface Type: MI2C, SPI, EUSART
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Package / Case: PDIP-8
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 3-4:
Legend:
x0Ch
x0Dh
x1Ch
x1Dh
x00h
x01h
x02h
x03h
x04h
x05h
x06h
x07h
x08h
x09h
x0Ah
x0Bh
x0Eh
x0Fh
x10h
x12h
x13h
x14h
x15h
x16h
x17h
x18h
x19h
x1Ah
x1Bh
x1Eh
x1Fh
x20h
x6Fh
x70h
x7Fh
x11h
Unimplemented
Read as ‘0’
70h – 7Fh
BANK 8
Accesses
STATUS
PCLATH
INTCON
FSR0L
FSR0H
FSR1L
FSR1H
WREG
INDF0
INDF1
BSR
PCL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
= Unimplemented data memory locations, read as ‘0’.
PIC12(L)F1840 MEMORY MAP, BANKS 8-23
x8Ch
x8Dh
x9Ch
x9Dh
xEFh
x80h
x81h
x82h
x83h
x84h
x85h
x86h
x87h
x88h
x89h
x8Ah
x8Bh
x8Eh
x8Fh
x90h
x91h
x92h
x93h
x94h
x95h
x96h
x97h
x98h
x99h
x9Ah
x9Bh
x9Eh
x9Fh
xA0h
xF0h
xFFh
Unimplemented
Read as ‘0’
70h – 7Fh
BANK 9
Accesses
STATUS
PCLATH
INTCON
FSR0L
FSR0H
FSR1L
FSR1H
WREG
INDF0
INDF1
BSR
PCL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
x0Ch
x0Dh
x1Ch
x1Dh
x00h
x01h
x02h
x03h
x04h
x05h
x06h
x07h
x08h
x09h
x0Ah
x0Bh
x0Eh
x0Fh
x10h
x11h
x12h
x13h
x14h
x15h
x16h
x17h
x18h
x19h
x1Ah
x1Bh
x1Eh
x1Fh
x20h
x6Fh
x70h
x7Fh
Unimplemented
BANK 10
Read as ‘0’
70h – 7Fh
Accesses
STATUS
PCLATH
INTCON
FSR0L
FSR0H
FSR1L
FSR1H
WREG
INDF0
INDF1
PCL
BSR
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
x8Ah
x8Bh
x8Ch
x8Dh
x8Eh
x9Ah
x9Bh
x9Ch
x9Dh
x9Eh
xA0h
xEFh
xFFh
x80h
x81h
x82h
x83h
x84h
x85h
x86h
x87h
x88h
x89h
x8Fh
x90h
x91h
x92h
x93h
x94h
x95h
x96h
x97h
x98h
x99h
x9Fh
xF0h
Unimplemented
BANK 11
Read as ‘0’
70h – 7Fh
Accesses
STATUS
PCLATH
INTCON
FSR0H
FSR1H
FSR0L
FSR1L
WREG
INDF0
INDF1
PCL
BSR
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
x0Ah
x0Bh
x0Ch
x0Dh
x0Eh
x1Ah
x1Bh
x1Ch
x1Dh
x1Eh
x00h
x01h
x02h
x03h
x04h
x05h
x06h
x07h
x08h
x09h
x0Fh
x10h
x11h
x12h
x13h
x14h
x15h
x16h
x17h
x18h
x19h
x1Fh
x20h
x6Fh
x70h
x7Fh
Unimplemented
Read as ‘0’
BANK 12
70h – 7Fh
Accesses
STATUS
PCLATH
INTCON
FSR0H
FSR1H
FSR0L
FSR1L
WREG
INDF0
INDF1
PCL
BSR
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
x8Ah
x8Bh
x8Ch
x8Dh
x8Eh
x8Fh
x9Ah
x9Bh
x9Ch
x9Dh
x9Eh
x9Fh
xA0h
xEFh
xF0h
xFFh
x80h
x81h
x82h
x83h
x84h
x85h
x86h
x87h
x88h
x89h
x90h
x91h
x92h
x93h
x94h
x95h
x96h
x97h
x98h
x99h
Unimplemented
Read as ‘0’
BANK 13
70h – 7Fh
Accesses
STATUS
PCLATH
INTCON
FSR0H
FSR1H
FSR0L
FSR1L
WREG
INDF0
INDF1
PCL
BSR
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
x0Ah
x0Bh
x0Ch
x0Dh
x0Eh
x0Fh
x1Ah
x1Bh
x1Ch
x1Dh
x1Eh
x1Fh
x6Fh
x7Fh
x00h
x01h
x02h
x03h
x04h
x05h
x06h
x07h
x08h
x09h
x10h
x11h
x12h
x13h
x14h
x15h
x16h
x17h
x18h
x19h
x20h
x70h
Unimplemented
Read as ‘0’
BANK 14
70h – 7Fh
Accesses
STATUS
PCLATH
INTCON
FSR0H
FSR1H
FSR0L
FSR1L
WREG
INDF0
INDF1
PCL
BSR
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
x8Ah
x8Bh
x8Ch
x8Dh
x8Eh
x8Fh
x9Ah
x9Bh
x9Ch
x9Dh
x9Eh
x9Fh
xA0h
xEFh
xF0h
xFFh
x80h
x81h
x82h
x83h
x84h
x85h
x86h
x87h
x88h
x89h
x90h
x91h
x92h
x93h
x94h
x95h
x96h
x97h
x98h
x99h
Unimplemented
Read as ‘0’
BANK 15
70h – 7Fh
Accesses
STATUS
PCLATH
INTCON
FSR0H
FSR1H
FSR0L
FSR1L
WREG
INDF0
INDF1
BSR
PCL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—